• Strange traveling spur problem seen in ADF4113HV

    Dear Analog Engineering Community,

    I am using the ADF4113HV to generate a phase locked signal on 7.784-7.786GHz from a 48MHz crystal reference.

    The simplified loop circuit is

    The settings are as shown:

    The current setting resistor is 4.7Kohm.

  • ADF4113HV initialized using the Initialization Latch Method

    Hi,

                    We are using a ADF4113HV, and previously thought it was a ADF4113 for one product.   In reading through the data sheet for the ADF4113HV, we discovered that the initialization latch is not touched or described.  The user guide for the ADF4113HV describes…

  • Comment on FAQ: Why use a PLL architecture that supports High Voltage VCOs?

    Dear App. Eng,

    I would like to use an ADF4113HV PLL in my DDS driven synth.

    I found in datasheet that Vp range is 13.5...16.5V. I have a max. 10V only.

    Q:

    Can I power the charge-pump by 10V? What kind of degradation is possible in PLL performance…

  • Why can I detect a large RFout/2 signal from RFout port, whose power isn't negligible

    Dear all,

    I used ADF4113HV and HMC738/HMC739 to form an RF sensor.

    A very large RFout/2 signal can be detected from RFout port.

    Although I used 50 ohm impedance to absorb RFout/2 output.

    Some details are shown in the photos.

    The substrate is FR-4, and…

  • RE: Mysterious behavior (ADF4350)

    Thanks for your replay

    I am using a TCXO 10MHz(FOX 926B) as a reference for my system. and I have used it in a different

    system with ADF4106 ADF4110 & ADF4113HV and it worked very nice without any problem

    but the problem appear here with ADF4350…

  • ADI PLL Int-N v7 software

    This software supports:

    ADF4001, ADF4002, ADF4106, ADF4107, ADF4108, ADF41020, ADF4110, ADF4111, ADF4112, ADF4113, ADF4113HV, ADF4116, ADF4117 and ADF4118.

    Operating systems: Windows XP, Vista and 7 (32 and 64 bit) compatible.

    Connection method: CyUSB…

  • RE: Generation of LO using ADF4106 and V950ME08-LF

    The ADF4106 evaluation board only supports VCO tuning voltages up to 5.5 V. If you want to get tuning voltages up to 9.5 V you will need an active filter. Your active filter would have an op amp to gain the tuning voltage up to 9.5 V. You will need to…

  • FAQ: Why use a PLL architecture that supports High Voltage VCOs?

    Q.

    Why use a PLL architecture that supports High Voltage VCOs?

    -------------------------------------------------------------------------------------------------------

    A.

    Although Analog Devices makes PLLs such as the ADF4350 which include integrated…

  • TAGS LIST: Clock and Timing

    LTC6953
    LTC6955
    LTC6957-1
    HMC6832
    HMC7043
    LTC6950
    LTC6954
    HMC987
    AD9576
    AD9508
    HMC1035
    HMC988
    HMC1033
    HMC1034
    HMC1032
    HMC1031
    ADN4670
    ADCLK944
    ADCLK950
    ADCLK948
    ADCLK846
    ADCLK954
    ADCLK946
    ADCLK854
    AD…
  • RE: 非常实用、超详细的锁相环常见问题解答~

    问题:锁相环系统的相位噪声来源有哪些?减小相位噪声的措施有哪些?

    答案:参考晶振(TCXO,VCXO)和R分频,PLL电荷泵,压控振荡器(VCO),N分频。锁相环系统的相位噪声来源于四个部分,参考输入,反馈分频1/N,电荷泵,VCO。这四部分贡献项可以用公式来表示。

    锁相环相位噪声贡献项模型

    对来说,系统闭环增益为低通特性,所以在环路带宽内,参考输入的相位噪声和N分频的噪声占很大比例(所以相同的输出频率,通过改变鉴相频率的方法并不会改善带内的相噪,因为参考源并未变化)。同样对Scp