My customer used ADF4113.
Also, I've corrected the error of circuit diagram as red mark.
First you need to verify it there is any communication between your PIC and the ADF4113. Try any/all of the following:
The Max Vcp is set by by the charge pump power supply ( Vp ) and in the case of ADF4113 the max voltage of Vp is 6V so Vcp can drive a VCO with a tuning voltage of up-to 6V
If the required tuning voltage of the VCO is 2.9V for an output frequency of…
on our new design board we've mounted the PLL Synth ADF4113 .
Unfortunately I don't find the linux IIO device driver for this chip. (I've already used adf4351 and I've found the driver on analogdevicesinc/linux · GitHub repo)
My customer has designed MUXOUT pin of PLL IC in digital lock detection mode, as shown below because of the difference in power level.
She was asked to comment of ADI on the design.
She has a problem that the muxout output is rarely high on unlock…
i have a experiment in which i need to fix R and N, so that Fpfd would change continuously, Ref in sweep (1 MHz to 200Mhz) nd RF IN (200MHz to 4 Ghz ) what should be the optimum value of R and N to do so ?
That is a mistake in the software. The Sync and Delay bits should actually be hidden. They apply to the ADF4110, ADF4111, ADF4112, and ADF4113 which use the same piece of evaluation board control software.
Just set them to 0 and I'll removed them in…
Do you still need the old version 4.2 ? I had a customer ask for this yesterday for an old ADF4113 eval board. I have posted it on our ftp site for him to download. So I will leave it up there for a few days if you want it. The link is ; ftp://ftp.analog…