• ADF4112 Fvco

    Hi,

    I am currently reviewing the ADF4112 fVCO. We would like to study if we can simulate the FSK feature in ADF4112

    Following equation is the VCO frequency:

    fVCO = [(P × B) + A] fREFIN/R

    Output frequency is generated by A&B counter, R divider…

  • ADF4112

    I am conused withe the descriotion in the ADF4112 datasheet. Could anyoneone clarify and give me any advice?

    In the ADF4110/ADF4111/ADF4112/ADF4113 Rev,C datasheet on page 3, the Reference Input Sensitivity is specified as 0.4/AVDD V p-p min/max for…

  • ADF4112 Operational Differences in Programming

    Hi,

    I have several questions In the Rev C datasheet, page 20 (and 17).

    - In the section - DEVICE PROGRAMMING AFTER INITIAL POWER-UP - is 3 methods.

         - Initialization Latch Method

         - CE Pin Method

    and - Counter Reset Method

    I'd like added clarification…

  • ADF4112 DVdd at MUXOUT is low

    Hi all,

    I am using EV-ADF411XSD1Z to test ADF4112. I try to see the DVdd value at MUXOUT port. But the signal is 2V instead of 3V which is the real DVdd provided to the chip. I also use a voltage meter to measure the DVdd at T9 test point, it is 3V.…

  • ADF4112 R Counter output is not square wave

    Hi,

    I am using EV-ADF411XSD1Z to test ADF4112. I use the onboard frequency reference(10MHz). When I check the R counter output at MUXOUT port. The signal is some spike waves instead of square wave(like the figue attached). And so as the N counter output…

  • Delay definition and performace of the ADF4112 software tool

     

    the upper figure is the software tool capture screen of the ADF4112.

    at this figure, In-band phase noise of the ADF4112 is dependent on delay value. when the delay is '1', phase noise performance is good but when the delay is'0',phase noise is degraded…

  • ADF4112 jittered at the frequency it was designed to lock, can anyone help please?

    Hi experts,

    My PLL built with ADF4112 is not working well. Loop filter components calculated by "ADIsimPLL" was used, with a few slight modifications according to standard resistance and capacitor values.

    I used a external VCO, average tunning…

  • ADF4112 无法完全锁定,VCO输出在设计频率处跳动

    技术专员和坛友们,我在使用ADF4112锁定时出现了无法完全锁定的情况,希望大家能给我一些建议,谢谢!

    具体情况如下:

    我利用ADIsimPLL仿真了一个锁相环,并且按照它计算出的环路参数焊接环路滤波器,具体设计参数及仿真结果如下:

    设计频率 鉴相频率 环路带宽 相位裕度 VCO灵敏度 电荷泵电流
    2598MHz 1MHz 100KHz 45° 100.1MHz 5mA(VP=5V)

    在实验中,发现VCO的输出频率能够从初始的2.375GHz迅速被拉至设计频率2.6GHz处…

  • RE: Ad4360-7 phase noise

    You could consider the ADF4112 with an external VCO. These tend to be lower power.

  • ADF41**系列是否支持RF差分输入?ADF4112SPI要求和410*有多少区别

    ADF410*和411*系列支持差分输入么,看datasheet上的结构示意图应该是可以,还是说RFINB只能接地?

    还有我之前用来写ADF4107的SPI程序用到ADF4112上没效果,看datasheet上的描述,411系列和410相比是少写一个function latch就行

    时序图是一样的,请问ADF4112的写寄存器有没有什么其他的要求

    是不是这个顺序?

    上电

    写initial latch

    写R

    写AB

    有点急,请不吝赐教