• ADF4111 Initialization

    I'm hoping that someone can confirm my initialization procedure for the ADF4111.  I've attached two different methods.  One is by using the CE pin and the other is via the Initialization latch.  I can't get it to lock and there absolutely 0V on the…

  • RE: Obsolete PLL Replacement

    Unfortunately, we have no PLLs that are drop-in replacements for that part.

    You may be interested in similar PLLs. Possibly the ADF4117 or ADF4111.

  • RE: ADF4111 Programming information

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • ADF4111 Ref input requirements



    I wish to know to know the performance of ADF4111 PLL with respect to Clipped sine wave reference vs pure sine wave reference. What is the differences in terms of performance like Phase noise, harmonics with respect to above two Ref inputs. Please…

  • RE: ADF4110 Prescaler

    Hi, at new PCB a make this prescaler for 500 / 1000

    ADF4111 work from 137.5MHz(may be lower, but a can't check) to 1.4-1.-8GHz while the upper limit of her 1.2GHz

    ADF4107 work up to 7 - 7.5 GHz

    Work with: ADF4106, ADF4107, ADF4110, ADF4111, ADF412…

  • ADIsimPLL : Crystek VCO with ADF4111 Question


    I am attempting to simulate a design using a Crystek VCO (CV55CL0120-0130) and an ADF4111. I would like a single output frequency of 125MHz using a reference of 44.8MHz. However, no matter what I seem to use for the parameters, ADIsimPLL gives…

  • RE: ADF4116 and "Delay" and "Sync" bits

    That is a mistake in the software. The Sync and Delay bits should actually be hidden. They apply to the ADF4110, ADF4111, ADF4112, and ADF4113 which use the same piece of evaluation board control software.

    Just set them to 0 and I'll removed them in…

  • RE: Using N, R divider for frequency division

    Yes, the input sensitivity and slew rate. You will need to scale down the amplitude. You can do this by placing a resistor (~100 ohm) between the two differential signals. Both signals should have have a series capacitor. See image.

    You will need…

  • ADI PLL Int-N v7 software

    This software supports:

    ADF4001, ADF4002, ADF4106, ADF4107, ADF4108, ADF41020, ADF4110, ADF4111, ADF4112, ADF4113, ADF4113HV, ADF4116, ADF4117 and ADF4118.

    Operating systems: Windows XP, Vista and 7 (32 and 64 bit) compatible.

    Connection method: CyUSB…

  • ADF4112

    I am conused withe the descriotion in the ADF4112 datasheet. Could anyoneone clarify and give me any advice?

    In the ADF4110/ADF4111/ADF4112/ADF4113 Rev,C datasheet on page 3, the Reference Input Sensitivity is specified as 0.4/AVDD V p-p min/max for…