• ADF4110 compare edge

    Hi

    Does the ADF4110 compare the rising edge of REF and the rising edge of RFinA and align their phases, or does the ADF4110 compare the falling edges of REF and the falling edge of RFinA and align their phases?

    Best regards

    N.Kokubo

  • About CP output of ADF4110

    Hello
    I have a question about the output of the ADF4110 charge pump.
    When the signals are input to REFIN and RFINA and locked, the CP output may be fixed to High or Low when the RFINA input is lost.
    I want to fix everything to High under this condition.

  • ADF4110 RF_IN_A and RF_IN_B Differential drive

    Hello,

    RF_IN_A and RF_IN_B of ADF4110 are differential inputs with 500ohm resistance fixed at 1.6V. Figure 29.
    Table 4. Pin Function Descriptions are shown as follows.
    RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.

  • ADF4110 minimum frequency of REFin and RFin

    Hi

    I'm a DFAE in Japan. Our customer would like to know the minimum frequency of REFin and RFin. We understand the slew rate has to keep >30V/us for RFin for lower than 80MHz and 100V/us for REFin for lower than 5MHz. What is the lower limit of…

  • ADF4110 TYPICAL PERFORMANCE CHARACTERISTICS

    Hi all,

    In the datasheet @ ADF4110/ADF4111/ADF4112/ADF4113: RF PLL Frequency Synthesizers Data Sheet (Rev. F),

    Typical performance characteristics are only for ADF4113 data.

    Is ADF4110 @ 540MHz data available?

    Best regards

    sss

  • ADF4110 min RF input frequency at VDD=5V

    Please let us know if you can use ADF4110 under the following conditions.


    ・ A VDD = DVDD = 5V,
    ・ RF frequency 60MHz ~ 100MHz
    Please let me know if you can use it.

    The RF input frequency is in the datasheet table specifications
    A VDD = DVDD = 3.0V and 5.…

  • Regarding the maximum absolute rating of ADF4110 VP and A VDD

    Hi,

    datasheet P6 Table 3.

    The datasheet specifies VP to be -0.3V to 5.5V for A VDD.
    Under transient conditions such as when the power is turned on, VP <A VDD.

    Is there any relaxation condition in a short time?

    I look forward to hearing from you.

  • ADF4110, how to read out the latch data ?

    we can only write date to the chip ??  the datasheets only gives the timing of write . 

    how to read data from the chip ? 

    and, these is a error in the datasheets : 

  • RE: ADF4110失锁

    This question has been closed by the EZ team and is assumed answered.
  • ADF4110 可以脱离单片机工作吗?

    看了一个贴子:

    The ADF4110 will start to lock the loop after a write to the AB counter latch.

    Your sequence should be something like this:

    1. Power up ADF4110 and VCO - VCO is output is some frequency between its output limits.
    2. Program ADF4110 Initialization Latch…