Unfortunately there is no IBIS model for ADF4002. The closest part to ADF4002 which has IBIS model is ADF4106. You can use ADF4106 IBIS model for reference.
ADF4106数据手册中第四页 PN SYNTH = PNTOT − 10 log PFD − 20 log N.
PFD=100MHz，N=17，PN SYNTH=-223,计算得到 PNTOT=118.
1.我选用-150dBc@1kHz的100MHz晶振，我的ADF4106输出1.7GHz的相噪最好能达到多少（@1kHz）;ADF4106d的Normalized Phase Noise Floor
–223 dBc/Hz typ （PLL loop B/W = 500 kHz, measured at 100 kHz offset）。
2.ADF4106数据手册中第四页 PN SYNTH = PNTOT − 10 log F PFD − 20 log N. ，其中 PNTOT 是多少？
I am designing a pll using ADF4106. Plz tell me how to program it using PIC18F4550.
I am designing a PLL using adf4106 and ROS-1631-119+ to generate single frequency of 1500MHz . ref clock is 60MHz.I used ADIsimPLL to generate loop filter parameters.But the Charge pump Pin of adf4106 is showing low voltage of 0.55v and if remove…
Assuming your frequency is fixed at 4920 MHz, I recommend the Int-N part, ADF4106: www.analog.com/adf4106
Your loop will require an external VCO.
Does your reference signal meet the requirements in the Reference Input section of the KSN-3940A+ data sheet?
There are some tests you can do to make sure if you are correctly programming the ADF4106.
First write the 3 register values you have above…
I am trying to generate LO using ADF4106 and V950ME08-LF.
I am using development board of ADF4106 and SDP.
When i am configuring the part for 4450MHz it is fine but when i am try to generate 5089MHz it is not going more than 4489MHz.
The input circuit of the ADF4106 is biased at VDD /2, so if you are using the same supply to your CMOS output crystal as the ADF4106, then you can connect directly using case 2, however if the crystal supply is different to the ADF4106, then…
And the EVAL-ADF4106 could output 155MHz?