As per datasheet,ADDI7013 pixel rate is 75Mhz at https://www.analog.com/en/products/addi7013.html#product-documentation.
Please let me know, where 65Mhz clock as mentioned?
I will forward this to the ADDI7013 expert.
The ADDI7013 specifies 200mV typical for the differential output swing, but the minimum can be less than 200mV. I don't know what the FPGA's receiver threshold is, whether this is OK or not.
Yes, the ADDI7013 can also operate at 20 MHz or 30…
We have tried to operate ADDI7013 and
found a problem that simulation result is not applied to device (ADDI7013).
Please advice to us to solve this problem.
And please recommend another new advanced part (or replacement of ADDI7013).…
This is an AFE part which we haven't really handled on this forum.There is a separate community for High speed ADCs(CCD),Please post your questions here https://ez.analog.com/community/data_converters/high-speed_adcs.
I received question about power-up sequence of ADDI7013 from our customer.
The customer set the register according to "RECOMMENDED POWER-UP SEQUENCE" in the datasheet of ADDI7013. However H-CLOCK signals were not output after sending…
I try to obtain Hardware response ADDI7013 but only simulate response;
After simulate OK with the VisualTgIdeADDI7013 software, I try to obtain Hardware answer.
But no hardware Answer , not in Slave Mode, not in Master Mode. not with VD HD Synchro…
We use the new ADDI7013 Dual-Channel CCD Signal Processor to read a CCD linear image sensor. The sensor outputs only one line with 2048 pixels, divided into eight segments of 4 dummy pixels and 256 valid pixels (therefore we use the ADDI7013…