• RE: ADDI7013_CLI_datasheet

    Hi,

     As per datasheet,ADDI7013 pixel rate is 75Mhz at https://www.analog.com/en/products/addi7013.html#product-documentation.

     Please let me know, where 65Mhz clock as mentioned?

    Thanks,

    Poornima

  • RE: IOVDD supply voltage about ADDI7013

    I will forward this to the ADDI7013 expert.

  • RE: Receiver for  Analog Front end reduced range lvds output

    The ADDI7013 specifies 200mV typical for the differential output swing, but the minimum can be less than 200mV. I don't know what the FPGA's receiver threshold is, whether this is OK or not.

    Yes, the ADDI7013 can also operate at 20 MHz or 30…

  • ADDI7013 timing output?

    Hi everyone,

    We have tried to operate ADDI7013 and

    found a problem that simulation result is not applied to device (ADDI7013).

    Please advice to us to solve this problem.

    And please recommend another new advanced part (or replacement of ADDI7013).…

  • RE: Assembly language of ADDI7013.

    Hi,

    This is an AFE part which we haven't really handled on this forum.There is a separate community for High speed ADCs(CCD),Please post your questions here https://ez.analog.com/community/data_converters/high-speed_adcs.

    Thanks,

    Poornima

  • RE: ADDI7013 operation and configuration

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • ADDI7013 Power-up Sequence

    Hello,

    I received question about power-up sequence of ADDI7013 from our customer.

    The customer set the register according to "RECOMMENDED POWER-UP SEQUENCE" in the datasheet of ADDI7013. However H-CLOCK signals were not output after sending…

  • Not Hardware answer after ADDI7013 programmation

    Hello,

    I try to obtain Hardware response ADDI7013 but only simulate response;

    After simulate OK with the VisualTgIdeADDI7013 software, I try to obtain Hardware answer.

    But no hardware Answer , not in Slave Mode, not in Master Mode. not with VD HD Synchro…

  • ADDI7013 - HD/VD, CLPOB and SYNC_DELAY

    Greetings all,

    We use the new ADDI7013 Dual-Channel CCD Signal Processor to read a CCD linear image sensor. The sensor outputs only one line with 2048 pixels, divided into eight segments of 4 dummy pixels and 256 valid pixels (therefore we use the ADDI7013…

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