• RE: Recommendations for PCIe 3.0 clock generator / Fanout?

    Hi Wireb,

    We have the ADCLK954 which has 2 inputs and 12 LVPECL outputs with 75fs of additive broadband jitter. Would a LVPECL swing ac-coupled into your receiver work for your system?  You would have to terminate the ADCLK954 outputs external to the…

  • ADCLK954 - IBIS Model

    Hi,

    Where can we get IBIS model for ADCLK954?

    Is it available on website?

  • ADCLK954 delay temperature coefficient

    Hello!

    According to datasheet of ADCLK954 it has delay temperature coefficient of 50 fs/C (quite exciting!). To prototype ADCLK954 before using in developing device I made a small PCB with it and measured parameters of interest. In particular, I measured…

  • RE: ADCLK944/948 - low frequency clock input

    Hi Meir,

    The ADCLK944 operates up to 6.2GHz and the ADCLK954 operates up to 4.5GHz.  There is no minimum input frequency limitation.  I have posted two images below that show the additive jitter that each buffer will add to your reference input with respect…

  • RE: ADCLK925 Max. V_IH

    Hi Charles,

    It would be clearer if both datasheets were like the ADCLK954. The author of the ADCLK925 datasheet was trying to specify the input voltages in terms of a ground-referenced, single-ended signal. This was done to hopefully make it easier to…

  • ADCLK954输出频谱各通道相差很大


    通过频谱仪测试ADCLK954各通道的宽频带频谱,发现输出不同通道之间差异较大,导致用不同通道的时钟进行ADC采样时,有效位相差2位。同一片芯片的3个典型频谱如下图所示,从下图可以看出,相同测试条件下,频谱不一样,经过系列验证,这个的确是ADCLK954自身输出结果,非外部走线等引入,也试过多个芯片,都存在类似现象,请问是什么原因导致?

    时钟和DDS(存档问题贴专区)

  • RE: high speed clock bus distribution

    Hi Donald,

    The phase noise performance required at each PCBx will help to choose the right clocking products.  Do you have a phase noise or jitter target?  If you already have an 80MHz oscillator, you could use a fanout buffer with 12 outputs such as the…

  • RE: Ultra low skew clock distribution

    Dear Chao,

    The best that we can offer is 3x AD9520s in zero delay mode. While it's true that it's about 500 ps of static phase offset variation, that is a 6-sigma number over process, temp, and voltage.  If the temperature and voltage is controlled…

  • Clocking a AD9910

    Hello,

    I am using a AD9956 to generate a 500MHz clock (CML) from an ultra stable 10MHz source. This clock signal should be distributed to different AD9910 DDS  (this chip because of the parallel capabilities). On the website I could find a LVPECL clock…