• ADCLK954 Power Dissipation

    In Table 4 of the ADCLK954 datasheet, the Typ and Max power supply currents are listed. In the "Test Conditions/Comments" column, it says "Static." What exactly does this mean with regard to the outputs? Are all the outputs terminated? Are they all open…

  • ADCLK954 - IBIS Model


    Where can we get IBIS model for ADCLK954?

    Is it available on website?

  • ADCLK954 delay temperature coefficient


    According to datasheet of ADCLK954 it has delay temperature coefficient of 50 fs/C (quite exciting!). To prototype ADCLK954 before using in developing device I made a small PCB with it and measured parameters of interest. In particular, I measured…

  • ADCLK954输出频谱各通道相差很大



  • RE: Recommendations for PCIe 3.0 clock generator / Fanout?

    Hi Wireb,

    We have the ADCLK954 which has 2 inputs and 12 LVPECL outputs with 75fs of additive broadband jitter. Would a LVPECL swing ac-coupled into your receiver work for your system?  You would have to terminate the ADCLK954 outputs external to the…

  • RE: ADCLK944/948 - low frequency clock input

    Hi Meir,

    The ADCLK944 operates up to 6.2GHz and the ADCLK954 operates up to 4.5GHz.  There is no minimum input frequency limitation.  I have posted two images below that show the additive jitter that each buffer will add to your reference input with respect…

  • RE: ADCLK925 Max. V_IH

    Hi Charles,

    It would be clearer if both datasheets were like the ADCLK954. The author of the ADCLK925 datasheet was trying to specify the input voltages in terms of a ground-referenced, single-ended signal. This was done to hopefully make it easier to…

  • RE: high speed clock bus distribution

    Hi Donald,

    The phase noise performance required at each PCBx will help to choose the right clocking products.  Do you have a phase noise or jitter target?  If you already have an 80MHz oscillator, you could use a fanout buffer with 12 outputs such as the…

  • RE: Ultra low skew clock distribution

    Dear Chao,

    The best that we can offer is 3x AD9520s in zero delay mode. While it's true that it's about 500 ps of static phase offset variation, that is a 6-sigma number over process, temp, and voltage.  If the temperature and voltage is controlled…

  • RE: Clock distribution recommendation

    Dear dsiaf,

    We have 1:12 fanout buffers like the ADCLK954 (LVPECL) and ADCLK854 (LVDS) that are extremely low jitter and low skew: