• ADCLK944 + PLL

    Hello,

    For my project i need a clock generator which has an low jitter(up to 100 fs) on the one hand and a frequency range from 500 MHz to 1800 MHz on the other hand. I need the clock generator for ADC, DAC and FPGA. I think about ADCLK944 as an clock…

  • ADCLK944 Skew

    Hi Experts,

    When I read the datasheet of the clock fanout chipset such as ADCLK846 or ADCLK944, it tells the max and typical skew between channels or between parts (several ps), so the skews are constant values bewteen power cycles or variable but within…

  • ADCLK944 and LTC5589

    Dear Sir:

    We want to use ADCLK944 as LO fanout, but LTC5589 is single LO.

    May I termination 50 ohm on un-used LVPECL outputs?

  • ADCLK944, ADL5385 & AD8347

    Hi

    I have a design which uses a ADCLK944 to provide fanout for local oscillator to two AD8347's and two AD5385's in the frequency range 900-2200MHz and all powered at 3.3V. All of the components are on one PCB and maximum track length is around 60mm…

  • ADCLK944 Unconnected Outputs

    I am using 3 of the 4 outputs on the ADCLK944.  Must I terminate unconnected outputs?

  • ADCLK944/946 - DC-coupled single ended inputs

    Hello,

    the datasheet of the ADCLK944 and ADCLK946 states that they are able to handle single ended DC-coupled input signals. In the datasheet under the "input termination options" section (page 11 of Rev. B datasheet) there is no figure that showes how…

  • HMC432 to Drive ADCLK944

    Can I use the HMC432 to drive the ADCLK944? I am not 100% sure what the output of the HMC432 is. I believe it's clipped sine. 

  • ADCLK944: 3.3V CMOS input

    Hello,

    How should we connect CLK, CLK-B, VT and Vref pins of ADCLK944 when we input 3.3V CMOS clock? Is this OK? Vref=open, VT=open, CLK-B=GND and CLK=3.3V CMOS signal input.

    Best Regards,

    Akira

  • ADCLK944 phase noise performance @ 6.4GHz

    Hi experts,

    From my project, I need to fanout high performance clocking outputs @ 6.4GHz. On the ADCLK944 datasheet, it only shows the phase noise performance @ 1 GHz. Its noise floor is about -150dBc/Hz for fin = 1GHz. What is the estimated phase noise…

  • adclk944有关参数疑问

    各位:想请教大家有关dc output characteristics 和Differential Output Voltage Swing 参数问题

    1.在adclk944的datasheet的p3中有参数1:Output Voltage, Single-Ended ,VOH − VOL, 为600~960 mv

    其中Output Voltage, Single-Ended ,VOH − VOL, 为600~960 mV

    2.在adclk944的datasheet的p7中有参数2…