Hello Akira-san,
Yes. However, my previous recommendation is for a normal clock signal.
Interfacing DC-coupled 3.3V CMOS into the ADCLK944 is a bit of a challenge.
In order for the input receiver to work properly, it's best if the VIL is >=1.1V.…
Thank you for quick reply. I decedied to use ADCLK944. But I just need 2 differential output. Can you suggest me how to terminate unused outbut of ADCLK944. A schematic represantation cab be perfect.
Serdar
Hello,
For my project i need a clock generator which has an low jitter(up to 100 fs) on the one hand and a frequency range from 500 MHz to 1800 MHz on the other hand. I need the clock generator for ADC, DAC and FPGA. I think about ADCLK944 as an clock…
I would suggest that you use two ADCLK914 parts instead of the ADCLK944. The swing is larger on the ADCLK914 than the ADCLK944. The ADCLK944 min swing of 1.2V meets the AD9739 min input swing requirement of 1.2V, but it leaves no room for PCB loss or…
My name is Meir and I am DFAE.
One of my castomers is interested in ADCLK944/948 clock distributor due to his low jitter and low skew performance. The input clock frequency range: 1Hz - 100MHz with a rise time of 10nsec.
My questions are:
I am use a 3.3V LVCMOS clock (single-ended) connect to ADCLK944 input.
The ADCLK944 datasheet said "The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs".
That's mean we …
Hi Experts,
When I read the datasheet of the clock fanout chipset such as ADCLK846 or ADCLK944, it tells the max and typical skew between channels or between parts (several ps), so the skews are constant values bewteen power cycles or variable but within…
Take a look at ADCLK944. While this device is specified as a clock distribution chip, it can also be used to split and distribute an LO.
您好！
您可以看一下ADCLK944/946/948/950/954。
There are a variety of parts, including the ADCLK944 and AD9508.
It really depends on what you need.
-Paul Kern