• ADCLK914 - 10MHz input - best approach

    Hello ADI team,

    the ADCLK914/905 datasheets clearly specify the input slew rate vs the output jitter. If one has a low frequency sinewave signal like 10MHz, what is the best approach to feed the input of the ADCLK914?

    The 10MHz sinewave clock has a…

  • ADCLK914 Equivalent Circuit

    Hello,

    I am working on a design using the ADCLK914. There is a section in the datasheet that shows what I think is a simplified equivalent circuit:

    I am doing some modelling using LTSpice to investigate some issues I am seeing with my implementation…

  • AD9789 Can I use ADCLK925? Instead of ADCLK914

    Hello

    I will design two AD9789, so I need two clock source. Clock is 2.4GHz.

    But ADCLK914 output is one port. 

    I found ADCLK925. ADCLK925 have one port input and two port output.

    Can I use ADCLK925? 

    Block Diagram

    Thank you

  • RE: ADCLK914 output impedance

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • 关于ADCLK905、ADCLK914无法正常工作的问题

    我想通过时钟buffer芯片为AD9957正交调制上变频提供方波参考时钟,我的时钟参考电路是利用ADF4351将10MHz晶振变频到需要的40.8MHz,然后通过ADCLK905对信号整形,作为AD9957的参考时钟输入。

    但目前的问题是ADCLK905一直没有整形的作用,如下图。

    目前只是将前级的信号进行了放大,并没有整形作用。上升下降时间与数据手册上的80ps还差了很远。不知道是什么原因。

    我的输出端接是采用的应用手册里面的端接。

    后级链接的是AD9957.

    示波器用的高阻探头…

  • ADCLK914输出功率过小,求指导!急!急!急!

    工程师:

    你好!

       我们正在使用贵公司的ADCLK914BCPZ芯片为AD9789提供参考输入时钟,严格按照ADCLK914芯片手册和AD9789的DEMO板电路设计,发现ADCLK914输出功率过小,后对ADCLK914单独进行测试。测试方法如下:

    1、用信号源给ADCLK914输入信号,信号输入端的连接方式如下图:

    2、输出连接到频谱仪上,输出电路如下图:

    在CLKP端有一个SMA母座测试点;

    3、信号源输入的时钟频率2.4G,功率从-4到+4dBm的单音信号,频谱仪测试ADCLK914输出功率在…

  • Clocking the AD9789: ADF4150 + ADCLK914 or ADF4150 alone?

    Hello,

    A couple of years ago we designed a PCB prototype using the DAC AD9789 clocked by a 2340 MHz VCO from RFMD squared up by the ADCLK914. The VCO was locked to an external 10 MHz reference using the PLL ADF4153. The designed met the specs by far…

  • Clock problem with ADCLK925 and AD9695/AD9739

    Hello

    I am using AD9695 and AD9739 with an ultrascale FPGA, on custom board.

    We have no problem with the design, until we load a high consumption bitsream into the FPGA.

    When the a full FPGA is loaded, the input clock (1280MHz) is no longer detected by…

  • Driving the clock of AD9739 DAC

    I'm using the AD9739 DAC device and according to its datasheet, the best way to
    drive its clock is by using the ADCLK914 (HVDS) driver. Can I use the ADF4350
    to drive the ADCLK914? What is the best way to interface between the RF output
    of…

  • AD9739_CLK input model and little output power

    I used ADCLK914 to drive the DACCLK according to description mentioned in the
    datasheet. However, I found when AD9739's clock pins are connected to CLKP and
    CLKN, there seemed to be a voltage degradation at the DACCLK input. Therefore,
    I would…