Hello,

I am working on a design using the ADCLK914. There is a section in the datasheet that shows what I think is a simplified equivalent circuit:

I am doing some modelling using LTSpice to investigate some issues I am seeing with my implementation…

In the datasheet, the 'Output Resistance' is listed as 250 ohm.  Please clarify, is this differential impedance?

Thanks!

Hello

I will design two AD9789, so I need two clock source. Clock is 2.4GHz.

But ADCLK914 output is one port. 

I found ADCLK925. ADCLK925 have one port input and two port output.

Can I use ADCLK925? 

Block Diagram

Thank you

Hello,

A couple of years ago we designed a PCB prototype using the DAC AD9789 clocked by a 2340 MHz VCO from RFMD squared up by the ADCLK914. The VCO was locked to an external 10 MHz reference using the PLL ADF4153. The designed met the specs by far…

工程师：

你好！

   我们正在使用贵公司的ADCLK914BCPZ芯片为AD9789提供参考输入时钟，严格按照ADCLK914芯片手册和AD9789的DEMO板电路设计，发现ADCLK914输出功率过小，后对ADCLK914单独进行测试。测试方法如下：

1、用信号源给ADCLK914输入信号，信号输入端的连接方式如下图：

2、输出连接到频谱仪上，输出电路如下图：

在CLKP端有一个SMA母座测试点；

3、信号源输入的时钟频率2.4G，功率从-4到+4dBm的单音信号，频谱仪测试ADCLK914输出功率在…

我想通过时钟buffer芯片为AD9957正交调制上变频提供方波参考时钟，我的时钟参考电路是利用ADF4351将10MHz晶振变频到需要的40.8MHz，然后通过ADCLK905对信号整形，作为AD9957的参考时钟输入。

但目前的问题是ADCLK905一直没有整形的作用，如下图。

目前只是将前级的信号进行了放大，并没有整形作用。上升下降时间与数据手册上的80ps还差了很远。不知道是什么原因。

我的输出端接是采用的应用手册里面的端接。

后级链接的是AD9957.

示波器用的高阻探头…

I made PLL Module using ADF4350 and DAC Module using ADCLK914 and AD9739A.

Because PLL Module and DAC Module is so far way, I use ADCLK914 for clock restoration.

DAC Module is work. It is good.

Now, I will revision DAC Module to include ADF4350.

Hello

I am using AD9695 and AD9739 with an ultrascale FPGA, on custom board.

We have no problem with the design, until we load a high consumption bitsream into the FPGA.

When the a full FPGA is loaded, the input clock (1280MHz) is no longer detected by…