• RE: Clock Level AD9789

    Hi danf,

    thank you very much for your feedback.

    Do you think, it is possible to replace the ADCLK914 with the ADCLK944,

    since the ADCLK914 isn't even listed anymore under the clock

    distribution devices?

  • Driving the clock of AD9739 DAC

    I'm using the AD9739 DAC device and according to its datasheet, the best way to
    drive its clock is by using the ADCLK914 (HVDS) driver. Can I use the ADF4350
    to drive the ADCLK914? What is the best way to interface between the RF output…
  • AD9739A Clocking

    I made PLL Module using ADF4350 and DAC Module using ADCLK914 and AD9739A.

    Because PLL Module and DAC Module is so far way, I use ADCLK914 for clock restoration.

    DAC Module is work. It is good.

    Now, I will revision DAC Module to include ADF4350.

  • RE: ADCLK914 output impedance

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • RE: AD9789 clocking

    It is mandatory to drive the 9789 with 1.4Vpp, like from an ADCLK914.

  • RE: no-OS code of AD9379A?


    I noticed that the pads of the mentioned components are already on the position of the narrow pads closer to the ADCLK914.

    After I saw the schematic of the board, I noticed that the output clock of adf4350 is not connected to any ports. Does it mean…

  • RE: Jitter specifications of ADN4661

    Hello Tak,

    Those are the two best parts for the lowest additive jitter contribution.

    In terms of wiring, it is best practice to place the buffer as close as possible to the converter. The layout for the evaluation boards are available online for your…

  • RE: AD9739, two device synchronization and their clocking input

    I would suggest that you use two ADCLK914 parts instead of the ADCLK944. The swing is larger on the ADCLK914 than the ADCLK944. The ADCLK944 min swing of 1.2V meets the AD9739 min input swing requirement of 1.2V, but it leaves no room for PCB loss or…

  • RE: CLK distributer with CML outputs

    Hi Meir,

    Is their any frequency translation requirement or is the goal only to distribute a single frequency?

    The only true CML clock buffer that we have is the ADCLK914.  This is only a 1:1 buffer.

    ADCLK914 datasheet and product info | Ultrafast, SiGe…

  • ADCLK914输出功率过小,求指导!急!急!急!