• RE: Jitter specifications of ADN4661

    Hello Tak,

    The engineer responsible for the ADCLK parts has offered this information:

    "The ADCLK905 and the ADCLk914 are the high performance parts, however their performance can degrade as input slew rate decreases.

    See figure 12 in the ADCLK905…

  • RE: CML to 1.2V single ended interface

    Hello Jordi,

    I'm not sure if your question pertains to the ACLK905 input or output. I'm guessing the output.

    In order to determine if the ADCLK905 will work, you will need to review the VIH/VIL specs for chip being driven by the ADCLK905. It…

  • RE: AD9914 Reference clock polarity swapping.

    Hi KennyG

    I am using ADCLK905BCPZ as a REFCLK buffer for AD9914 DDS. In my PCB if i put both the ic in top plane the clock signals are crossing each other. So can i connect the CLK of the AD9914 with CLK# of the ADCLK905 and CLK# of the AD9914 with CLK…

  • ADF4351 Wideband Clock Generation

    I'm planning to use an ADF4351 to generate clocks across its entire frequency range (35 Mhz - 4.4 Ghz). The part needs to generate a fast serial clock for a SERDES block on an ASIC and a divided version of the same clock for transceivers on an FPGA.…

  • RE: Clock problem with ADCLK925 and AD9695/AD9739

    Because of a bad design and very high consumption of FPGA, DC/DC regulators output is VERY noisy on on FPGAs 0.95V rail. The noise is so high that it pollutes the 1280MHz clock. We have implemented the second solution (ADCLK905 on AD9695 instead of ADCLK914…

  • RE: ADF4110 Channel Spacing

    Hello ,

    The ADCMP553/ ADCLK905 will not divide the input signal.....why not use the R counter to divide the input reference signal ?

    Regards,

    Brigid.

  • RE: AD9528 VCXO_IN clock type

    The AD9528 does accept a sine wave in the VCXO_IN. In this mode, the VCXO_INB pin should be AC grounded and the receiver mode should be set to differential. Table 4 in the AD9528 datasheet explains the minimum input amplitude and the minimum input slew…

  • RE: HMC704 input reference frequency

    Thank you.It is a pity that I  have no such condition. I am using a clock driver ADCLK905 for sharping 1MHz sinewave to get a high slew rate.I think this would be better .

  • RE: ADF4108 REFin Characteristic Question

    Hello Brian,

    We have used the ADCLK905 to square up the edges with good results, ac couple into it, and use a transformer to ac couple the differential output to the PLL REFIN.

    Regards,

    Brigid.