• ADAU7002

    Hi

    I have a question ADAU7002.

    Please tell me how you are doing downsampling when PDM → PCM conversion ADAU7002 inside.
    (Thin out data? Low pass filter? Etc.)

     

    Best Regards

    HOD

  • ADAU7002 + ADAU1701

    Hi Sir,

    My end customer have a design==> PDM to I2S(ADAU7002) and I2S in ADAU1701 headphone output.

    For my check,

    ADAU1701 MCLK can use internal crystal and LRCLK/BCLK need output to ADAU7002,

    Can you teach me register window and schematic how…

  • ADAU7002 overshoot?

    Hi

    I use the ADAU7002 to convert PDM signal to i2s.

    When I turn on the power I get some kind of "overshoot" at the signal output for about 1 sec (image attached)

    Is this normal behavior?

    Can anyone explain the reason of that and how to…

  • ADAU7002 Current

    Hi

     

    I have a question ADAU7002.

    Please tell me the operating current of the ADAU7002.

    Currently IOVDD = 2.2 V is input to the power supply voltage and I thought that the operating current was 0.85 mA from the data sheet.
    Is it that SDATA 4.5 mA and PDM_CLK…

  • ADAU7002 Timing Diagram

    Hi,

    ADAU7002 datasheet doesn't contain a timing diagram between BCLK, LRCLK and PDM_CKL. I need it because I want to synchronize a multiple sources at same time (simultaneously) using TDM8 mode. Could anyone provide me a diagram where several ADAU7002…

  • ADAU7002 Question

    The phenomenon as shown in the figure occurs immediately after BCLK input start in ADAU 7002.

    The output is flat for 4 ms to 16 ms (50 to 180 samples at 11 kHz), is it normal?

     




    Also, when sampling sound with constant frequency and output, you can se…

  • ADAU7002 Eagle library

    HI,

    Anyone has eagle library for ADAU7002?

  • ADAU7002 PCLK is not generating

    Hi All,

    I am using ADAU7002 chip for PDM to I2S conversion. I am using PDM digital mic (MP34DB02) for input.

    I checked BCLK and LRCLK. BCLK(Bit clock) and LRCLK(SYNC) frequency are proper and their values are 1024MHz and 16KHz respectively. But ADAU7002…

  • ADAU7002 PDM output clock issue

    HI, 

    We are using ADAU7002 to covert from PDM to TDM input. The condition is as below.

    Our configuration is as below, and the TDM LRCK/BCK from host is 48k/12.288MHz TDM mode.

    But we found the PDM_CLK output from ADAU7002 is 1.5MHz only, it should be 3…

  • ADAU7002 SMT Reflow Profile Document

    Dear Sir,

    Dear All:

    Is there any  ADAU7002 relevant "SMT reflow profile" can provide to me refer? On ADI's website where can download these document? Would you please provide ADAU7002 “SMT reflow profile”?

    Thanks a lot.

     

    Jane