• ADAU1977/ADAU1978/ADAU1979 PLL and Clock settings, when sampling rate is lower than 32kHz

    Hi,

    Please let me ask how to configure PLL and Clock when the sampling rate is lower than 32kHz.

    For example, when sampling rate is 16kHz on the ADAU1978,
    how can we decide SAI_CTRL0.FS and PLL_CONTROL.MCS values, and MCLKIN frequency?

    Depending on the sampling…

  • ADAU1979

    Hello,

    Is there an 8 channel version of the ADAU1979 ? Need balanced analogue inputs, so the ADAU7118 is not applicable.

    Thanks,

    Hanif

  • Is it possible to 50KHZ sample rate in ADAU1979?

    Hi All,

    While looking into the ADAU1979  datasheet I found it is only possible to set 48KHZ sample rate. So can anyone exaplain is it possible to configure 50KHZ sample and how to set this configuration PLL and SERIAL PORT CONTROL REGISTER 1.

  • RE: Questions regarding ADAU1979

    This question has been closed by the EZ team and is assumed answered.
  • RE: ADAU1979 PLL and serial audio port clocks

    This question has been closed by the EZ team and is assumed answered.
  • ADAU1979

    ADAU1979 can be operated up to fs = 192 kHz. The typical performance characteristics are shown at datasheet only for

    fs = 48 kHz. Are there typical performance characteristics available for fs = 192 kHz?

    If not, what degrading by scaling the 48 kHz…

  • ADAU1979 Output Data Format

    Can you please provide a description of the output data format for the ADAU1979? In this post, it specifies that data is two's complement, and I do not see anything in the datasheet regarding the format. We cannot seem to calculate the appropriate voltage…

  • RE: questions regarding ADAU1979

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • Confusion of adau1979 datasheet

    Hi,

          I read the adau1979 datasheet with some confusion, as follows:

          

        As above, tABH: min 10ns

                         tABL: min 10ns

                         tABDD: max 18ns

       In I2S mode, the i2s data delayed by 1 BCLK, that

                         tABDD = tABH + tABL = min 20ns

            but tABDD need less than 18ns,Did…