• ADAU1978 IBIS model request

    Hi Team,

    Our customer needs a IBIS Model of ADAU1978 for SI Analysis.

    Could you please help me on this ?

    Best regards,


  • About the filter function of ADAU1979 and ADAU1978


    I have a question about the filter characteristics of ADAU1979 and ADAU1978.
    In the data sheet P4, there is a description about pass band that is 0.475 × fs at fs = 48kHz, but should I think about 0.475 × fs at fs = 96kHz and fs = 192kHz as well…

  • RE: Is PLL filter always needed in ADAU1978?

    Hi Dave, yes, the answer is quite late and we already discovered that PLL is needed.

    We have had additional trouble with phase synchronisation of two ADAU feeded with the same TDM signal. Thanks to the support of your colleague Salvatore Napolitano (Italy…

  • ADAU1978 Digital DC high-pass filter


    I'm using ADAU1978, can you please clarify the use of the digital DC high pass filter configured in register 0x1A bits 0-3?

    Also, how is it working with enabling DC calibration (in register 0x0E bit0) and DC subtraction configuration?


  • ADAU1978 clipping status


    Regarding the ADC CLIPPING STATUS REGISTER - how often does this register update? Is it set when clipping is detected and cleared when read? does it update every time interval? 

    If clipping is detected - should I see a value of 0x7FFFFF on the output…

  • RE: ADAU1978 at 192 KHz: noise at high frequencies


    Apologies for missing this item. I am not sure if it still relevant to you that this question will be answered, However, we are clearing up some open items in our community and ensure that any query is located on its proper community as others who have…

  • ADAU1977/ADAU1978/ADAU1979 PLL and Clock settings, when sampling rate is lower than 32kHz


    Please let me ask how to configure PLL and Clock when the sampling rate is lower than 32kHz.

    For example, when sampling rate is 16kHz on the ADAU1978,
    how can we decide SAI_CTRL0.FS and PLL_CONTROL.MCS values, and MCLKIN frequency?

    Depending on the sampling…

  • ADAU1978 TDM problem


    my ADC sends wrong datas on TDM, this is an example :

    The BCLK and LRCLK signals are sent by a FPGA, they don't seem too bad (probed with a 2GHz active probe) :

    LRCLK is sampled by the ADC on rising edge, here are the ADC registers :


  • RE: ADAU1978 configuration

    Hi Dave,

    Sorry for delayed response. I am trying to store I2S data by simply opening a file with the .wav extension. Then the microcontroller that i am using has i2s peripheral on it,so i simply do a i2s receive and then try to store the data which is…