Hi,

I would like to apply the ADAU1977 for multi analog input as shown in the picture below

May I know is this possible? And, what about the I2S output? Can I select the output from which two analog channels?

And about the software GUI to configure…

Do you have any device drivers (linux or microcontroller) available or in development for the ADAU1977 Quad ADC?

Dear Support,

                      I look for ADAU1977 Digital volume control

                      information at D.S but not found

 pls advice

                      Thank you in advance

                    Miguel Liber

For my customer Factem that is starting a project with the ADAU1977 audio ADC, I have a question regarding the MCLK pin (pin 7)….

He won’t use the MCLK input clock and will be in slave mode with the PLL locked on the LRCK clock input . Can you tell us…

One of our customer is struggling to get the ADAU1977 driver register with no error in the kernel.

After adding some print traces into the driver code, it seems the error comes from the driver complaining that the configuration is missing the dai_name…

Hello,

I have a few problems integrating the ADAU1977 with the help of the Linux driver from Analog Devices and I would be happy if someone can help me.

At first a little overview about my system:

Hardware:

     - NXP i.MX 8MN Eval-Board

     - ADAU1977 is connected…

Hi All,

I'd like to set 128kHz sample rate but no information on Table 10. in the data sheet.

Does the ADAU1977 support 128kHz sample rate?  If it does, please let me know what registers I should set to get 128kHz sample rate.

Regards,

Kazu

Hello all,

ADAU1977 Data Sheet doesn’t have any information about its load current.

Could you please provide it for me?

■Back ground of the question

In my system, I connected ADSP21489 to 4 ADCs(ADAU1977).

I need to know if ADSP21489s driving capability…

Hello all,

I have a question about tABDD on ADAU1977.

The ADAU1977 data sheet table 6 on p.8 says that the tABDD(SDATAOUTx delay from BCLK falling) is 18 ns at maximum.

The Figure 2. Serial Output Port Timing on p.9 shows tABDD in Left justified mode…