• RE: ADAU1966A initialization question

    I am using the ADAU1966A. Here are snippits of the schematic.

  • ADAU1966A I2S Multiplexing


            I have a special need now .

            I need to make a multi-channel audio product .

            I want to know how many analog audio channels can I output if I input one channel  I2S to adau1966a. (for example ,DSDATA1 input)

            Because I want to get multichannel audio…

  • ADAU1966A Register Programming Sequence

    We are using  ADAU1966A  in system design with direct master clock mode by following clock sequences. 

       MCLK : 16 MHz

       DBCLK: 1 MHz

       DLRCLK: 31.25KHz 

       sampling rate FS : 31.25 KHz

       I2S Left Right justified

    We need help with programming the registers, for…

  • RE: Question about ADAU1966A

    Hello lefeng,

    This is a huge topic for discussion and there have been many articles written about this subject. 

    This depends on the actual use of the capacitor. In general, we used a lot of aluminum electrolytic capacitors because they are still a good…

  • RE: ADAU196XAZ test, i can't get a digital input 24bit signal by the sigmastudio or the ARWB

    Hi Dave

    thaks for your reply.

    in the DAC board adau1966a, i set the sampling clock in EVAL-ADAU196XAZ to be 192kHz, and the adau1966a DAC oversampling rate select the 126 x fs DAC oversampling.also tne internal board  PLL of adau1966a select the MCLK as…

  • Comment on ADAU1966: If using a direct MCLK can I leave LF and PLLVDD pins disconnected?

    1.I am using ADAU1966A Audio DAC in slave mode. MASTER CLOCK is driven from FPGA, So the LF pin is unconnected. kindly suggest how to terminate the LF pin.
    2. In theory of operation of ADAU1966A, it is stated that…
  • Using SDP-B With ADAU1966A


    I would like to know if it is possible to use SDP-B with EVAL-ADAU1966AZ, which is the evaluation module for ADAU1966A.

    We have one board of EVAL-ADAU1966AZ, which has a compatible connector to assemble SDP-B, but we don't find the EVAL-ADAU1966AZ…

  • ADAU1966A PLL Locking Issue

    Hi Dave,

    We are using  ADAU1966A  in system design with direct master clock mode ,

    MCLK : 3 MHz (768 X Fs )

    sampling rate FS : 3.91 KHz

    DBCLK & DLRCLK are measured at the IC pin. The following values are ,

    DBCLK : 137.1389 KHz

    DLRCLK : 4.28855 KHz


  • RE: ADAU1966a StandAlone mode

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • ADAU1966A Maximum & Minimum Audio Input Sampling Rate

    Hi All,

    I'm going to use this ADAU1966A in my upcoming project for an audio application. We're having 3 different audio bandwidth in our application.

    (a) The first type will have 10KHz audio bandwidth with 31.25KHz sampling rate. 

    (b) The second…