Our customer met an issue, their product(speaker) using ADAU1451 had finished development stage and MP for a while, but their end customer returned the failures set to them (2 sets in this Feb, 3 sets in May of end, total 5 failures sets) from…
Thank you Dave for your answer.
It's a bit complicate to implement the patch directly in the DSP as we are not using internal blocks but routing directly ASRC to SDIN and SDOUT with registers.
We are polling for ASRC unlocked status and mute signal…
We are designing a digital audio console with ADAU1451 DSP
We need to use the Aout3 TDM 8 output of ADAU 1451 to get four AES-3 outs. How can we demux the 8 channels to use four DIT 4096 Texas stereo serial audio to AES converters? Or do you know another…
I am working on a linux driver to interface with a ADAU1451 that is running a program developed in sigma studio. I have exported the header files and am able to interact with the device over spi but I find the SigmaStudioFW.h quite lacking. The generated…
Is it possible to create a loop in Sigma studio to execute low level bloc (multiply, add, and so on) ?
I have discovered the issue. it is not related to SW i was able to get I2S (L/R channels) using two outputs from 1372 working as well as TDM (4 channels) using 1 output from 1372 working.
can someone explain how to use the new multirate feature in SigmaStudio 3.12 and adau1451, upsampling is possible?
My project is running at fs48k, i need some process at 192kz , for example pass through FIR filter at 192
My next hardware…
请问下在Sigma 300里面使用硬件加速器slew，slew mode为RC type时，对应的time constant 与数据从当前值到目标值得时间有什么关系,或者说不同的time constant的值有什么用？
I have a problem when load the EQ parameters on ADAU1451.
I build a 28 band EQ. T
The first parameter address is: 0x002B //DM0
The second parameter address is: 0x600E//DM1
The third parameter address is: 0x0030
The fourth parameter address is:…
Our customer's project have four serial out from ADAU1451. OUT3 have independent BCLK/LRCK;
for layout board size and EMC concern, OUT1 and OUT2 share BCLK0/LRCK0 from OUT0 (PORT1 and PORT2 BCLK/LRCLK no layout, pin in open state).