I am writing for support of ADATE320 and ADATE209.
In our project, ADATE320 is uesd to realize 1.6 Gbps LVDS signal adjust.
Original LVDS signals comes from FPGA (Xilinx HP bank). There is my first
question, could you give us a circuit of typical…
1.According to ADATE209 datasheet Figure 13 CLC Disable and Enable, Showed CLC Enabled sign-wave amplitude small than Disabled, which result different than others.Is that correctly?
2. I can’t understand the Figure 14 chart, Are DROUT1 and DROUT2…
After a long time of no response to my previous question on the ADATE209,
I edited the contents of this post.
Does AnalogDevice support simulation model for ADATE209 device ?
From the product page, I cannot find any.
From the local sales, I heard…
Does ADI can provide ADATE209_Simulation Model(S-parameter)?
My customer need to above for a simulation ,tks!
I could get only the datasheet in the website. Is there more design guide, like tools for the register configuration,whitepaper about the mode in application, or the DMO board?
Thank you for taking interest in our ATE products. The AD53513 is a Quad Ultrahigh-Speed Pin Driver with High-Z and VTERM Modes. Given that, the closest which is now still in production is the ADATE209. To better help, can I have additional…