• ADA4897-1输出摆幅问题

    大家好,最近有一个项目打算采用ADA4897-1作为ADC驱动放大器,手动搭接了一个电压跟随器用于测试ADA4897-1,设计采用5V单端供电,信号发生器到运放采用交流耦合的方式,同时在同相端增加一个2.5V偏置电压,使用示波器查看输出波形,发现在输入信号幅度较小时,电路工作正常,但是当输出幅度大于4.2V时,信号出现顶端截止的现象,但是按照手册上说的,其输出摆幅应该在0.2-4.8之间,而且我用pspice仿真时,确实是在4.8V时才截止的,不知道大家碰到过没有,期待您的回复!!

  • OP284 and ADA4897-1 and maximum PCB driving distance

    Hello experts

    Question and appreciate your advise:

    For a standard PCB (FR4, 4 layers 1.6mm pcb thickness, track of 0.254mm, with ground plane on the 2nd layer). point-to-point. and assuming termination is good. Signal source frequency is approx 1khz…

  • ADA4897-1损坏问题原因分析

    用ADA4897-1做反相放大,±5V供电,调试时用直流稳压电源供电,由于稳压电源没有使能功能,所以板子直接连在稳压电源上打开电源,结果三片4897全部损坏。又试了一次,又损坏了三个,但是同板子的JFET放大器没有损坏。由于板子需要器件的可靠性很高,所以想查清楚原因,麻烦各位朋友帮忙分析一下!

  • 【求助】ADMP401 加运放ADA4897-1 电路  Vref取值问题?

    ADMP401 加运放ADA4897-1 电路  Vref,这个参考电压应该取什么值?这个取值有什么要求呢?

  • 使用ADA4897-1出现大幅失调电压 ,怎么办?

    来自网友jeg 的提问

     

    我有一个标准反相放大器级Rf=100KRg = 10k (A = -10 V/V) 放大器采用+/-5V电源供电并且正输入端子连接到0V 引脚15为开路。 引脚8 (nDISABLE)也为开路。 非常简单的设置。

     

    问题是输出的DC失调为-2.2V除此以外行为与AC信号的预期行为相同。 尝试禁用引脚高电平,但没有效果。 在三个ADA4897-1器件上重复了此操作,结果全部相同。 在正输入与接地之间插入一个9kOhm的偏置补偿电阻之后,DC失调…

  • JPEG Processing - 4:2:2 v 4:2:0?

    My JPEG saga continue...

    I am using a BF561 single core to compress a 640x480 YUV 4:2:2 image into JPEG format, employing the ADI JPEG Library tools.  I am getting very poor performance compared with the reference results from the Spec Sheet.  The Spec…

  • ADV7842 4:2:2 DDR mode, ADV7393: Stanag3350 support?  (2)

    Hello Dave,

    I am facing problems with replies to your answer, so I am oppening a new dicussion with the same title.

    Please clarify your answer regarding STANAG support:

    2) As I understand it, this is the same as RS-343A/EIA-343A and none of our parts…

  • LTC6804-2 and LTC6811-2 reference voltage 1 and 2 at 0V.

    Hello,

    I installed 2x LTC6811-2 and then 1x LTC6804-2 on the same board and I don't have any voltage reference output at anytime. The functional diagram in the datasheets shows that VREF1 should be always present as it's generated from V+. VREF2 is not…

  • RE: Clock distribution to 2 DDSs (9913) and 2 ADCs (AD7769)

    Hi,

    the AD9577 is a good choice if the 40 MHz clocks to the AD9913 may not be phase aligned to the 40 MHz clocks to the AD7769.

    The AD9577 has two PLLs that are not recommended to work at the same frequency because  the jitter performance is degraded …

  • 2*2 MIMO setup

    Hello,

    Iam interested in implementing a MIMO 2*2 scenario where i will use 2 fpgas (1 as the transmitter and 1 as the receiver) where each one  will be connected with one AD-FMCOMMS3-EBZ.
    So the setup will be :
    FPGA_1 + AD-FMCOMMS3-EBZ_1 =Base stati…