• 最爱ADI放大器-ADA4692-2

    我们的变送器产品中用到放大器芯片对传感器探头信号进行预处理，因为是4...20mA接口，因此需要低功耗的放大器芯片。我们就选择了ADI的放大器ADA4692-2.

  • 最爱ADI放大器-ADA4692-2

    最爱ADI放大器-ADA4692-2 by songchenping

    我们的变送器产品中用到放大器芯片对传感器探头信号进行预处理，因为是4...20mA接口，因此需要低功耗的放大器芯片。我们就选择了ADI的放大器ADA4692-2.

  • RE: Voltage follower on ADA4692 cut of the signal

    Hi,

    The input voltage range of the ADA4692 needs a headroom of ~1.1V.
    Using supply of 3V, the max input could be only around 2V.

    Thanks and regards!

  • RE: Script file of ADV7611 for 24bit SDR 4:2:2 Mode 2 output

    Hi,

       In general the drive strength and trace impedance must match to reduce ringing

      The ringing is caused by a mis-match in the drive strength and trace impedance.  Try lowering the drive strength for the pin output or increasing the series resistor.Note…

  • JPEG Processing - 4:2:2 v 4:2:0?

    My JPEG saga continue...

    I am using a BF561 single core to compress a 640x480 YUV 4:2:2 image into JPEG format, employing the ADI JPEG Library tools.  I am getting very poor performance compared with the reference results from the Spec Sheet.  The Spec…

  • ADV7842 4:2:2 DDR mode, ADV7393: Stanag3350 support?  (2)

    Hello Dave,

    I am facing problems with replies to your answer, so I am oppening a new dicussion with the same title.

    Please clarify your answer regarding STANAG support:

    2) As I understand it, this is the same as RS-343A/EIA-343A and none of our parts…

  • ADV7403 Register Values for RGB Input and YUV 16bit 4:2:2 output

    Hi,

    I have a following script for a RGB input and YUV 422 output. 

    Reg Address Reg Data
    0x52 0x00
    0x53 0x00
    0x54 0x07
    0x55 0x0C
    0x56 0x94
    0x57 0x89
    0x58 0x48
    0x59 0x08
    0x5A 0x00
    0x5B 0x68
    0x5C 0x81
    0x5D 0x00
    0x5E 0x19
    0x…

  • LTC6804-2 and LTC6811-2 reference voltage 1 and 2 at 0V.

    Hello,

    I installed 2x LTC6811-2 and then 1x LTC6804-2 on the same board and I don't have any voltage reference output at anytime. The functional diagram in the datasheets shows that VREF1 should be always present as it's generated from V+. VREF2 is not…

  • 2*2 MIMO setup

    Hello,

    Iam interested in implementing a MIMO 2*2 scenario where i will use 2 fpgas (1 as the transmitter and 1 as the receiver) where each one  will be connected with one AD-FMCOMMS3-EBZ.
    So the setup will be :
    FPGA_1 + AD-FMCOMMS3-EBZ_1 =Base stati…

  • ADV7403 YUV 4:2:2?

    Can the ADV7403 output YUV 4:2:2 rather than YCbCr 4:2:2?

    Thanks.

    Chris