• ADA4665-2失调电压问题

    我一直在用ADA4665-2,现在遇到一个小问题,之前测试的信号是0~5V、0~10V的电压信号,此芯片的应用一点问题都没有。并且我也做过实验,用ADA4665-2只作为信号跟随时,其失调电压的确很低,进入ADC后,最低能识别到0.2V左右。但是如果我要测试的信号范围变为20~40mV时,在跟随后,再加一级放大的话,效果就不是很好了,是不是因为我采集的信号范围和运放所加的电源(0~10),导致被测信号落入失调电压范围内,或是接近失调电压造成的?

    我还要问两个问题:

         1.如果将电源电压变为正负电压…

  • ADA4665-2

    Hello

    I have a question about AD4655.

    Although there is description that the typical value of the slew rate of this device is 1V/μs, please tell me the upper and lower limits.

    I could not find it in the datasheet. 

  • ADI年度贺岁片——ADA4665-2放大器的应用

    ADI Annual New Year Film - Application of ADA4665-2 Amplifier by mengyun2801

            In the past, the digital circuit was mainly used. After changing the work, the design of the analog circuit was gradually increased. However, through the learning and understanding…

  • ADI年度贺岁片——ADA4665-2放大器的应用

            以前基本以数字电路为主,换了工作后,逐渐增加了模拟电路的设计,但是通过在ADI的学习和了解,这些也不是什么问题了,从简单的放大器应用,到放大器的特殊应用,基本上都有所了解了。之前利用AD4665-2做了一个数据采集放大电路,其轨到轨、低功耗和最低阈值很好的解决了我的特殊问题,随后又将其应用到电压基准输出电路,更是淋漓尽致的发挥其作用,ADI的芯片的确是很给力~~~

    下面是ADA4665-2的介绍:

            它是一款轨到轨输入/输出、双通道放大器,针对较低功耗预算设计进行了优化。25°C时,每个放大器的最大电源电流低至400μA…

  • JPEG Processing - 4:2:2 v 4:2:0?

    My JPEG saga continue...

    I am using a BF561 single core to compress a 640x480 YUV 4:2:2 image into JPEG format, employing the ADI JPEG Library tools.  I am getting very poor performance compared with the reference results from the Spec Sheet.  The Spec…

  • ADV7842 4:2:2 DDR mode, ADV7393: Stanag3350 support?  (2)

    Hello Dave,

    I am facing problems with replies to your answer, so I am oppening a new dicussion with the same title.

    Please clarify your answer regarding STANAG support:

    2) As I understand it, this is the same as RS-343A/EIA-343A and none of our parts…

  • LTC6804-2 and LTC6811-2 reference voltage 1 and 2 at 0V.

    Hello,

    I installed 2x LTC6811-2 and then 1x LTC6804-2 on the same board and I don't have any voltage reference output at anytime. The functional diagram in the datasheets shows that VREF1 should be always present as it's generated from V+. VREF2 is not…

  • RE: Clock distribution to 2 DDSs (9913) and 2 ADCs (AD7769)

    Hi,

    the AD9577 is a good choice if the 40 MHz clocks to the AD9913 may not be phase aligned to the 40 MHz clocks to the AD7769.

    The AD9577 has two PLLs that are not recommended to work at the same frequency because  the jitter performance is degraded …

  • 2*2 MIMO setup

    Hello,

    Iam interested in implementing a MIMO 2*2 scenario where i will use 2 fpgas (1 as the transmitter and 1 as the receiver) where each one  will be connected with one AD-FMCOMMS3-EBZ.
    So the setup will be :
    FPGA_1 + AD-FMCOMMS3-EBZ_1 =Base stati…

  • ADV7403 YUV 4:2:2?

    Can the ADV7403 output YUV 4:2:2 rather than YCbCr 4:2:2?

    Thanks.

    Chris