• ADA4500-2 - Driving an ADC

    Will the ADA4500 drive an Analog-to-Digital Converter?

     

    There are many considerations when driving an ADC.  A primary consideration is
    the noise and linearity of the amplifier driving the ADC. The effective
    resolution of an ADC is affected…
  • ADA4500-2 - Charge-pump noise affect

    Does charge-pump noise affect the signal quality of the ADA4500 output?

     

    The ADA4500’s charge pump operates at a very fast clock speed, varying between
    3.5 MHz and 5MHz over its supply voltage range. This high frequency does not
    show…
  • ADA4500-2 - Resistors around the amplifier

    What resistor values should I use around the amplifier?

     

    ADA4500 has a low voltage noise density of 14.5 nV/√Hz.  Placing a 1KΩ resistor
    with thermal noise of 4 nV/√Hz at the input of the amplifier increases total
    input referred noise…
  • ADA4500-2 - Output driven beyond one of the supply rails

    What happens if the output is driven beyond one of the supply-rail Voltages?

     

    The ADA4500 has been designed to accommodate output overload.
    Op amps typically are not designed to tolerate overload; they can take tens of
    microseconds to…
  • ADA4500 understanding load capacitance effects

    Hello,

    I'm using the ada4500 in a product design and have a questions regarding how load capacitance effects the part.  Could someone explain what exactly figure 37 in the data sheet means?  What is small signal overshoot and how do I apply that graph…

  • RE: Clock distribution to 2 DDSs (9913) and 2 ADCs (AD7769)

    Hi,

    the AD9577 is a good choice if the 40 MHz clocks to the AD9913 may not be phase aligned to the 40 MHz clocks to the AD7769.

    The AD9577 has two PLLs that are not recommended to work at the same frequency because  the jitter performance is degraded …

  • JPEG Processing - 4:2:2 v 4:2:0?

    My JPEG saga continue...

    I am using a BF561 single core to compress a 640x480 YUV 4:2:2 image into JPEG format, employing the ADI JPEG Library tools.  I am getting very poor performance compared with the reference results from the Spec Sheet.  The Spec…

  • ADV7842 4:2:2 DDR mode, ADV7393: Stanag3350 support?  (2)

    Hello Dave,

    I am facing problems with replies to your answer, so I am oppening a new dicussion with the same title.

    Please clarify your answer regarding STANAG support:

    2) As I understand it, this is the same as RS-343A/EIA-343A and none of our parts…

  • LTC6804-2 and LTC6811-2 reference voltage 1 and 2 at 0V.

    Hello,

    I installed 2x LTC6811-2 and then 1x LTC6804-2 on the same board and I don't have any voltage reference output at anytime. The functional diagram in the datasheets shows that VREF1 should be always present as it's generated from V+. VREF2 is not…

  • 2*2 MIMO setup

    Hello,

    Iam interested in implementing a MIMO 2*2 scenario where i will use 2 fpgas (1 as the transmitter and 1 as the receiver) where each one  will be connected with one AD-FMCOMMS3-EBZ.
    So the setup will be :
    FPGA_1 + AD-FMCOMMS3-EBZ_1 =Base stati…