• need footprint for CP-10-10 LFCSP package (ADA4062-2)

    I think there are a couple of things wrong with the suggested footprint for the CP-10-10 package that you can download from the first row of this table:


    ( The…

  • Need help to design a transimpedance using ADA4062

    I am designing a transimpedance using ADA4062-2(figure 1). The input signal contains 1kHz sine wave and 2kHz sine wave. My target is to measure the amplitude and the phase of 2kHz sine wave signal.

    As the signal is quite small, I decide to use the T…

  • ADA4062-4 spice mode

    Hello everyone

    I want to simulate my circuit  with LTspice, but can not find the model of ADA4062-4, does anyone know a similar spice mode to ADA4062-4?

    best ragards.


  • AD548B replacement is ADA4062

    Here is a customer who wants to know if the part AD548B is still in massive


    AD548 is an old part. It is better to use ADA4062 family instead.
  • RE: Script file of ADV7611 for 24bit SDR 4:2:2 Mode 2 output

    Hi Poornima,

    Actually 24 bit SDR 4:2:2 mode(0x8A) has been used here and least significant 2 bits of YCbCr are discarded. Yes we tried the different drive strength on that pins all are sinusoidal. 

    0x9A,0x14, 0x5E

    0x9A, 0x19, 0x8A

    0x9A, 0x33, 0x40


  • JPEG Processing - 4:2:2 v 4:2:0?

    My JPEG saga continue...

    I am using a BF561 single core to compress a 640x480 YUV 4:2:2 image into JPEG format, employing the ADI JPEG Library tools.  I am getting very poor performance compared with the reference results from the Spec Sheet.  The Spec…

  • ADV7842 4:2:2 DDR mode, ADV7393: Stanag3350 support?  (2)

    Hello Dave,

    I am facing problems with replies to your answer, so I am oppening a new dicussion with the same title.

    Please clarify your answer regarding STANAG support:

    2) As I understand it, this is the same as RS-343A/EIA-343A and none of our parts…

  • LTC6804-2 and LTC6811-2 reference voltage 1 and 2 at 0V.


    I installed 2x LTC6811-2 and then 1x LTC6804-2 on the same board and I don't have any voltage reference output at anytime. The functional diagram in the datasheets shows that VREF1 should be always present as it's generated from V+. VREF2 is not…

  • RE: ADV7403 Register Values for RGB Input and YUV 16bit 4:2:2 output


    Thank you for your reply.

      the resolution needed are mentioned below : 

    Below are the input resolutions to the ADV7403 chip:

    720x576i @ 50/25Hz(Class B)video resolution, Interlaced video input,RGB(STANAG Class B)
    720x480i @ 60/30Hz(Class C)video resolution…

  • 2*2 MIMO setup


    Iam interested in implementing a MIMO 2*2 scenario where i will use 2 fpgas (1 as the transmitter and 1 as the receiver) where each one  will be connected with one AD-FMCOMMS3-EBZ.
    So the setup will be :
    FPGA_1 + AD-FMCOMMS3-EBZ_1 =Base stati…