• question about AD9963 bist

    Dear sir,

            do you have any introdution about AD9963 bist? i see in the datasheet, BIST can generate two type waveform, one is PRN, the other is 0xa5a. but i see in the DAC port, it is a triangular wave when in 0xa5a mode;

            is it correct? i want…

  • AD9963-EBZ and Xilinx ML605

    Hello! I am a new member of this forum and I hope someone can help me solving a problem.

    I am working with "AD9963" Evaluation Board and using the "AD FMC adapter" to connect the board with the Xilinx FPGA virtex 6 ML605. I want to convert the digital…

  • AD9963 (M2K board) FPGA Reference Design


    I am currently working on developing a sensor evaluation system using Zedboard FPGA and AD9963 FMC board.

    We could boot-up Linux (from SD card with pre-loaded image) on Zedboard based on instructions available in Wiki page.

    Since there is no FMCOMMS2…

  • AD9963  时钟沿问题




  • AD9963   DLL配置问题






  • About AD9963 power distribution solution.

    Hi, I find the power solution of AD9963 EVM board AD9963-EBZ RevB Schematic is rather complex. There are 7 LDOs ( ADP3334ARZ ) employed in this design, as well as lots of magnetic bead placed on the power rails. I 'd like to know whether it is necessary…

  • AD9963-EBZ DAC output level

    Hi all,

    How many output typical level is the AD9963-EBZ DAC SMA output, with Full-ScaleCurrent 2mA ?

    DAC output circuit  at the EVB is configued by the 453 ohm registor and 9:1 transformer.

    Best regards,


  • AD9963-EBZ DPG Downloader “No Device Found”

    在我使用AD9963-EBZ开发板通过USB连接线与PC进行连接后,DPG Downloader软件中显示“No Device Found”,这是什么原因?

    而在AD9963-SPI软件中已经可以通过USB连接线对AD9963进行配置了,且我的操作步骤是严格按照start guide进行的。谢谢。

  • AD9963 DAC Common Mode Voltage

    How can one set the output common mode voltage of the DAC of AD9963. The full scale current is (Ifs) 2 mA and does it implies the common mode voltage level is  Ifs/2 * R.   I need to interface the DAC to another module which has the common mode range of…

  • AD9963 TX port sampling clock edge


    We have designed the TX digital interface according the datasheet, and generate the data timing so that the data is stable at positive sampling edge.. We set the bit TXCKI_INV to 1, but it is not stable. When clear the bit  TXCKI_INV, it is stable now…