• Current consumption of AD9957 in Full sleep mode

    Hello. I have one question. Please tell me.

    The AD9957 has a full sleep mode function, and power consumption in this mode is specified as typ=12mW.

    Is it possible to provide the data of each current value of "DVDD_I/O (3.3V) ,DVDD (1.8V) Pin, AVDD (3…

  • EVAL-AD9957 board for full external control

    hello  everyone; 

    I'am trying o use eval-ad9957 with full external control using spi (from fpga). any guidlines ? please 

    thanks for all 

  • AD9957 Matlab Model ?

    Is there a Matlab model of the AD9957 component (with filter taps and bit rounding operations in each stage) ?
    The link provided in a previous answer on this subject is no longer valid.

    Emmanuel

  • AD9957 spurious output

    Hi,

    we are using AD9957 in QDUC at 350 MHz and we have sample rate harmonic spurs on output, with a PDCLK 96 MHz rate

    for a 96 MHZ sample rate.

    In the plot in the AD9957 datasheet I don't see this kind of spurs, could you suggest us something to limit…

  • AD9957 BFI mode problem

    Hello,

       I'm looking for a help in setting up AD9957 in BFI mode.

    I've build my own project in which AD9957 is controlled though BFI interface by ZYNQ7000. Unfortunately I can't run properly AD9957 in BFI mode. When I set SINGLE TONE MODE device works…

  • AD9957 Output

    Hi, I am using the AD9957. I use the Blackfin mode QDUC. On the Q-channel I send 0x8000 and on the I-channel 0x0000. There is no output signal. But if I swap the data to I-channel 0x8000 and Q-channel 0x000 there is carrier visible? This is wierd. Can…

  • AD9957 TXENABLE vs Output

    Hello,

    I'm trying to use the AD9957 DDS chip with a microcontroller with an FPGA in between to assist with some clocking. My setup is currently:

    MCU -> FIFO -> AD9957 Evaluation board

    According to the datasheet, the TXEnable signal is used to…

  • AD9957 Phase Truncation

    Hi,

    From the AD9957 datasheet it is not possible to discern the size of the sin/cos lookup table.

    While the phase offset has 14 bits, they are MSB aligned with the phase akkumulator, which apparently has 32 bits, but it is nowhere mentioned how many bits…

  • 关于AD9957

    你好,ADI专家:

          我目前项目需求为输出8路150M中频,各路需要同步(输出相位差能相参),杂散优于60dBc;数据来源为FPGA,IQ数据,数据时钟100M,基带带宽低于30M,,目前DAC时钟为外部提供的800MHz。   

          问题1:通过ADI官网选型发现AD9957接口设计比较简单,想要选用,不知道这个DAC可否满足我的需求,,,多片同步是否可以实现相参。。。。

          问题2:ADI是否有更好解决方案,如直接可以单片实现双通道(AD9957一路一片,功耗也高),更低功耗,,的DAC可以满足我的需要…