Q 

1.Our design uses the two options described on datasheet page 30. I.e.
synchronizing with SYNC_IN and SYNC_CLK signals AND a single crystal driving
multiple (=16) AD9954s. Do you recommend using it this way?
2a.Datasheet section Synchronizing multiple…

FAQ

Porgrammable phase/amplitude dithering is listed in the AD9954 features on the front page of the datasheet, but nowhere in the datasheet is there a description of how to implement it, or what it does.  Please provide some guidance.

The AD9954 DDS core…

Q 

I have used AD9954 as a clock reference, but in the output of DDS, one spur
which frequency is N*Fxtal/4 (N is the PLL multiplier)exists, would you help me
how to eliminate this spur.

A 

The frequency that you refer to is equal to the SYNC_CLK…

Q 

What is the RELATIVE level of the DDS ""spurious"" at  DDS-Clock ( AD9954 at
400 MHz.) / 8 ,and DDS- Clock / 16 ?
( Ofcourse with no filtering but direct at R-DAC and single ended oputput )
Any measuremnts done ?
And are these…

Q 

The datasheet of the AD9954 specifies that DACBP should be decoupled to Ground.
It would make sense to me to decouple
it to the Analog Ground rather than the Digital Ground. It is not specified in
the datasheet.
Any more information about this…

Q 

how can I get the AD9954 evaluation software introduction.

A 

please see the attachment.

Q 

I would like to know what is the AD9954's power cunsumption for each state on
powerdown (refer to Table 9 of the datasheet, Rev.B

A 

Please see estimated results attached for the AD9954 power consumption in
different powerdown modes.
Recorded…

Q 

The limitation to AVDD +/-0.5V comes from the use of a transformer and the
device itself.

If I use a resistor the ouput compliance voltage windows will became AVDD to
AVDD-0.5V ?so half of it?

A 

The output voltage limitation is from the DAC itself…