• RE: What kind of logic is the CLKMODESELECT pin on AD9951 compatible with?

    It turns out the AD9951 and AD9954 are very similar devices. As such, the CLKMODESELECT pin on the AD9951 is NOT 3.3V tolerant (like the AD9954).

  • Eval kit for AD9951, AD9952, AD9953 and AD9954

    Does an Eval Board exist for the AD9951, AD9952, AD9953 and the AD9954?


    The family of DDS', AD9954, AD9953, AD9952 and the AD9951 use the same die,
    and the AD9954 has the most features.

    As sown here, the AD9954 can be used for evaluation…
  • AD9951

    In the pin function description for AD9951 IOUT, it is described  "should be biased through a resistor to AVDD"

    So whar is the resistor value?

      It seems there is no evaluation module for AD9951. I checked AD9954 EVM and found 25ohms for

  • AD9951 I/O UPDATE Synchrinization

    Is it possible for there to be a meta-stability issue if the I/O UPDATE signal is not synchronized external to the AD9951?

    If so, how would it manifest this issue with respect to the AD9951 operation.

  • Default value of CFR2 on AD9951 ??


    We are about to add support for the AD9951 on one of our products.

    We currently use a AD9954 on this board. At power-up the software reads the default value of the CFR2 register to verify that the DDS is fitted.

    With a AD9954 this default is 0x180000…

  • RE: AD9951 PLL Loop Filter Component Values

    The 0Ω resistor in the loop filter of the AD9951 Evaluation Board is correct.

    The LOOP_FILTER pin of the AD9951 has an internal 820Ω series resistor (for ESD protection), which essentially satisfies the 1kΩ mentioned in the pin description in the…

  • RE: DDS Synchronisation using FPGA as the controlling mechanism


    I don't have a particular FPGA to suggest but you can use the FPGA that you are most familiar with. The AD9951 serial I/O port can be easily interfaced to an FPGA. Unfortunately, we do not have any code available for programming the AD9951 using…

  • RE: Rset amplitude modulation in AD9951

    AN-423 is associate with the AD9850 and AD9851 parts. I do not have direct knowledge of it working exactly the same for the AD9951. However, I would think the concept would work. Here's one thing to note. The AD9951 and AD9850/51 both have a pin called…

  • DDS Synchronisation with FPGA as a Controlling Device

    Hi , I want to purchase AD9951 DDS chip to generate multiple signal frequencies in a synchronized manner. In this I want to use FPGA as a controlling mechanism for these DDS chips. What are the parameters I need to consider in selecting FPGA related to…

  • RE: AVDD and DVDD power consumption in AD9951

    I hooked up the AD9951 evaluation board with one DUT populated and measured the following supply currents. I clocked the AD9951 at 400MSPS. Note, the IDVDD current should be roughly linear with the clock rate.

    IAVDD = 41mA

    IDVDD = 43mA

    IDVDD_IO = …