• Cannot connect over USB to AD9915

    I am using two of the AD9915 devices in a single setup and am unable to connect to either over USB to the computer that has been integrated into the setup. However, it is possible to connect to both on an alternative computer (one that cannot be integrated…

  • Achieving optimal performance from the AD9914/AD9915

    Are there conditions that will help the part reach its best performance?


    Yes, if you can provide a digital power supply which holds to 1.8V+5%/-0%, and
    if you can keep the part cooled, you will get better performance than if you
    have a low supply…

  • AD9915 DAC


    I use serial mode and it can’t be configured; after working, the current of the 3.3V power supply is only 0.49A, and the 1.8V current is 0.23A. It looks like the DAC part is not working. Is there any solution to control the status of the DAC separately…

  • BPSK signal generation in AD9915

    Hello all,

    I want to generate a BPSK signal in the AD9915. Is it possible to generate the BPSK signal in AD9915?

    If yes, what's the way to generate it in GUI and as well as through SPI programming?

    #ad9914 #ad9915 #dds


  • AD9915 shows a frequency offset


    I use an Arduino Due (master) to control the AD9915 DDS board (slave) via SPI control.

    My Arduino code writes the correct definitions into the registers.

    For example, if I want to set up a profile frequency of 100.0 MHz. The entries in the reg…

  • AD9915 sinusoidal tone distortion (glitch in phase accumulator?) with Profile Mode and matched latency

    Hi all,

    I am using AD 9915.

    I'm using Profiles Modulation mode on the official eval board to generate Binary-phase shift keying Pulsed Radar signal 

    - Matched latency, auto clear phase accumulator enabled

    - Profile 0 Direct Switch null amplitude ,…

  • AD9915 SPI Timing


    On p. 6 in the datasheet of AD9915, in "Serial Port Timing" one can read

    SCLK 80 MHz

    SDIO to SCLK Setup Time 4.9 ns

    SDIO to SCLK Hold Time 0 ns


    SCLK Falling Edge to Valid Data on SDIO/SDO  78 ns

    When the SCLK period is 12.5 ns, how…

  • AD9915 SCLK pin

    Dear all,

    I am using AD9915 evaluation board. I have noticed that SCLK pin when FUNC pins are set for serial programming is high by default. When I connect DIO to the signal pin and the ground of the EVAL board and output pulse it never goes logic low…

  • AD9915 PLL无法锁定


    dds_data_ram[0]    <= 40'h02_00050C00;       // PLL CONFIG     CFR3:PLL倍频24倍,N设置为12                  

    dds_data_ram[1]    <= 40'h00_00010308…

  • AD9915 PLL won't lock above 2.4GHz, Very low DDS Output power


    I'm trying to setup the AD9915 with a double-ended crystal clock at 156.25MHz.

    I'm using a 2x Divider, and N=16 which should set the PLL output to 2.5GHz.

    Unfortunately After VCO Calibration and reading lock status bit, I'm not achieving…