Thanks for the clarification.
Hi,
There is no minimum or maximum frequency value for the external crystal according to the data sheet but the typical 25MHz value is required as the circuitry within the device is tuned to this specific frequency. Using different frequency value will…
Hi Louijie,
Per datasheet of AD9913, SYNC_CLK is an output of AD9913, then exact synchronization of multiple AD9913 requires that the SYNC_CLK output of multile AD9913 have same timing(rising/falling edge time) when they have the same REF_CLK input.
…Hi Tim,
Unfortunately, all our DDSs with frequency sweep does not have this kind of functionality.
Best regards,
Mark
What is the minimum reference clock frequency input for the AD9913, both with and without the PLL multiplier enabled?
Thanks.
Hi, on the AD9913, how much worse should the phase noise be when the PLL is engaged (2x multiplication) vs.
when it is direct fed? In this specific case:
Fref: 90 MHz = sysclk
vs.
Fref: 90MHz using PLL=2x, 180 MHz = sysclk
For a FIXED output frequency…
Hi all, how to connect the AD9913 chips for interfacing? Have any schematic diagram of the complete AD9913 chips module for me to refer?
Thanks!
Hello,
I can see in my design strange behavior linked to the profiles configuration on AD9913.The component configuration is:
16MHz input multiplied by 15 = 240MHz, switching mode, serial configuration (SPI 200kbps)
The issue is:
I configure profiles…
I have an AD9913 evaluation board and I'm trying to monitor the SYNC_CLK signal at the J2 connector. There is no signal at this connector, just +1.8VDC. I have also probed the SYNC_CLK pin at the AD9913 device and found the same result. What should…
Hello,
I'm searching for a DDS from Analog Devices and it seems like the AD9913 DDS meets our requirement.
However, in the datasheet below, it does not specify what is the minimum clock input frequency for the RefClkIn. Do you know what is the spec…