What is the minimum reference clock frequency input for the AD9913, both with and without the PLL multiplier enabled?

Thanks.

Hi, on the AD9913, how much worse should the phase noise be when the PLL is engaged (2x multiplication) vs.

when it is direct fed? In this specific case:

Fref: 90 MHz  = sysclk

vs.

Fref: 90MHz using PLL=2x, 180 MHz = sysclk

For a FIXED output frequency…

Hi,

we want to use 3 pieces of AD9913 on our application and keep the board complexity low.

Is it mandatory to issue a device reset via the MASTER_RESET pin or can the pin simply be grounded?

Thanks, Tom

Hello,

I can see  in my design strange behavior linked to the profiles configuration on AD9913.The component configuration is:

16MHz input multiplied by 15 = 240MHz, switching mode, serial configuration (SPI 200kbps)

The issue is:

I configure profiles…

Hey all - I have two AD9913 running from the same clock. Need a defined phase shift between them. I assume I can do this by,

1) Program the devices registers as required.

2) Use IO_UPDATE to load both devices at the same time (IO_UPDATE is routed to…

I have an AD9913 evaluation board and I'm trying to monitor the SYNC_CLK signal at the J2 connector.  There is no signal at this connector, just +1.8VDC.  I have also probed the SYNC_CLK pin at the AD9913 device and found the same result.  What should…

Hello,

I'm searching for a DDS from Analog Devices and it seems like the AD9913 DDS meets our requirement.
However, in the datasheet below, it does not specify what is the minimum clock input frequency for the RefClkIn. Do you know what is the spec…

Hi everyone,

My team and I have been working on a little RF-Controller project. The goal of the project is to produce a 3MHz signal , with serial programming, through the AD9913 from adjusting it's frequency tuning word (FTW). However, it doesn't seem…