• AD9912

    请问AD9912可以用LVDS差分时钟吗?

  • AD9912

    AD9912 的参考输入可以是正弦波吗?

  • AD9912

    Is it possible to generate frequency ramp using AD9912?

  • AD9912

    hello sir,

    i want to know how to lock the clock frequency in AD9912 when we apply input clock

  • AD9912


    请问AD9912在改变频率的时候能不能只设置频率控制字寄存器,而不更新其他寄存器实现变频,希望能够尽快得到解答。

    谢谢!

  • AD9912

    On page 5 of the AD9912 datasheet, under "SYSTEM CLOCK INPUT/SYSCLK PLL Bypassed/Input Resistance" the range is specified as 2.4 to 2.9 kohms differential.  But on page 21, Figure 47 the schematic for "SYSCLK BYPASSES" shows a 500 ohm resistor…

  • AD9912: multichip synchronization

    I hope to synchronize 32 pcs AD9912. But when we test with only 2 pcs of
    AD9912, the difference of output phase are variable each time after power on. I
    disabled the  CLK multiplier and provided 1GHz clock external, the update
    clocks…
  • AD9912 IO-UPDATA

    AD9912的IO-UPDATA信号,用寄存器配置的话,那外部链接的IO-UPDATA是置高还是置零,我试过没控制起。

  • AD9912问题

    我用AD9912做跳频系列,输入时钟是一个960M的时钟,项目需求输出是在480M+/-20M这个范围内以125K间隔跳变的时钟,调试过程中,发现跳频时钟是按需求输出了,但是从频谱上看,输出除了这个跳频时钟外,一直有一个480M的比较弱的时钟存在,请问这会是什么原因引起的,我另一块电路板能正常输出跳频系列时钟,没有这个480M的干扰出现。

  • AD9912

    What is the reason for a 250MHz minimum frequency for SYSCLK on the 9912 DDS? I would like to run it at 100MHz or lower.

    It seems peculiar that it would have a lower frequency limit. What sets the lower frequency limit? Thanks