i want to know how to lock the clock frequency in AD9912 when we apply input clock
I use AD9912. I need to make synchronization for AD9912 from external signal. AD9912 doesn't have SYNC IN pin. I use microcontroller to config AD9912. How is it avalibale to make it?
Hi everyone. I'm student.
I have one ATmega128A and three AD9912
1. 109Mhz fDDS of AD9912(HIGH)
2. 108Mhz fDDS of AD9912(MID)
3. 107Mhz fDDS of AD9912(LOW)
Every time turn off the power
Default between ad9912
phase is change and not same
i want to…
The AD9912 is a derivative of the AD9549. The AD9912 is DDS function in the AD9549.
I have attached the firmware and source code for the AD9549 evaluation board software. So, it's
for the AD9912 too.
I need to design a reconstruction diff lpf for my AD9912 the problem is that i don't have much board space available.
The only design I found is for a 7 pole filter.
I need it to pass a max freq of 200MHz.
Does anybody know a lower pole …
On page 5 of the AD9912 datasheet, under "SYSTEM CLOCK INPUT/SYSCLK PLL Bypassed/Input Resistance" the range is specified as 2.4 to 2.9 kohms differential. But on page 21, Figure 47 the schematic for "SYSCLK BYPASSES" shows a 500 ohm resistor…
What is the reason for a 250MHz minimum frequency for SYSCLK on the 9912 DDS? I would like to run it at 100MHz or lower.
It seems peculiar that it would have a lower frequency limit. What sets the lower frequency limit? Thanks