We use analog RGB signal (H,V,R,G,B) at 1280*1024 (60Hz).
There is about 34 ns jitter for first 120~130 lines of HSYNC from Pin NO 139.
Since then, Jitter of HSYNC is under 4ns and this value is OK for our use.
Was there issue like above…
Please let me know your advice about power sequence of VD, VDD and PVO.
Especially, please let me know your advice about power up of PVO (Clock Generator Power Supply).
My problem is tmds's clk can't lock good. I check the hardware and compare two board.
One is adv7441a, the other one is ad9887a (my another good DVI product).
1) I found that the problem is not edid because I cut off adv7441a's DDC…
Can you explain the project? AD9887A isn't recommended for new designs.
The AD9887A is an old part that we do not recommend you use in new designs and very limited support is available. ADV7842 is also a dual analog/HDMI receiver and is recommended for new designs. All it's support files are here: http://ez.analog…