• AD9874 -- How it works without voltage reference

    Hello,

    For project purpose, I expect to source LO and CLK with one 18MHz directly, which means I'll disable the LO synthesizer, the clock synthesizer, and the reference voltage. The IF input for the project is 15.75MHz. I made the following changes…

  • RE: IBIS Model

    Hello,

    I attached a the IBIS model of the AD9864 which is the same product as the AD9874 with the exception that its LNA/mixer bias level is fixed (vs programmable as AD9874).  While AD9874 is is LQPF (vs LFCSP for AD9864), the pinout/package dimensions…

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  • RE: AD9874 - SSI synchronization of multiply devices

    Hello Igor,

    The issue is that the CLKIN signal is generated the AD9864 PLL while the SYNCB signal is generated from the FPGA thus it may be more difficult to control the timing since SYNCB signal is not edge triggered.  In other words, when SYNC goes…

  • RE: Very low sensitive of AD9874

    Hello,

    It appears that you have R4/R5 installed when trying to measure the performance of the AD9874 on its own. Try removing these resistors so that "mixer observation" path is disconnected from the LC tank circuit since may be the cause of your problems…

  • RE: AD9864_74 Evaluation Board HELP??

    Hi,

    The AD9864/74 converter was aimed at single channel radios for 2G applications, and communications infrastructer designers used multiple radios in parallel to cover their available spectrum.  Today there are converters (see the AD9467) that can be…

  • RE: ADF4360-9 for generating a LO freq. Unacceptable Jitter?

    For APCO25, which has large close-in interferers, you should consider a single (or dual) conversion architecture with a decent IF filter and look at using the AD9864 or AD9874 IF subsystems and do the demodulation in software.

    VCOs for this application…

  • Issue with SPORT0 Receive Logic

    Hi:

      I'm new to BlackFin, and with using the SPORT Serial Interface.  Currently using the BF506F processor on the EZ-Kit.  Was able to configure the SPORT0 and jumper the Transmit and receive Sections together on the EZ-DSP to get simple loopback…

  • RE: AD9874 EVAL-BOARD CLK

    Hello,

    Equation for LOSC and COSC is provided above in figure 7a that you posted in original post.  This equation is an estimate but typically one needs to experiment a little to modify values such that the charge pump output (TP1) is around mid-supply…

    • attachFile.pptx

  • low output amplitude of AD9874

    Hello, I'm using AD9874 to receive signals around 2.65 MHz. The hardware is the AD9874 eval board. I'm using the external clock source and hung mixer mode to prevent LO. The output data format is 24 bits. I have low pass filters after the sampling.…