• AD9864 settling time

    It appears possible to pipeline readings through the AD9864 signal chain,  the next symbol can be presented to the input a couple of frames before the present reading starts to change as a result. From tests it appears to take around 11 frame periods to…

  • AD9864 process

    Is it SiGe-Bicmos or just RF cmos ?

  • AD9864 White Noise and Sampling Rate Questions

    Hello

    I have two questions regarding the AD9864.

    question 1
    Is there any white noise characteristic data for the AD9864?

    Question 2
    Please tell me the sampling rate when communicating AD9864 with SSI.

    We would appreciate it if you could reply.

    Best…

  • AD9864: CLK & LO drive levels

    Hello,

    For a project I am currently working on we would like to drive the AD9864 LO and CLK ports directly. 

    The clock generator which would generate the signals for this can output, amongst other options, LVDS and High Swing Differential Signalling …

  • moving clock synthesizer of ad9864 with high temperature

    hello support team

    we have a problem about clk synthesizer.

    when we tested ad9864 in my test room, every thing is ok and don't move the ad9864 clk synth.

    but when we go to field test (like as free space and In the vicinity of the sun) after a short…

  • RE: AD9864 FFT分析结果

    This question has been closed by the EZ team and is assumed answered.
  • AD9864 CLK INPUT

    We use an external generator (CMOS output VCTCXO) to drive AD9864 CLK input.

    We apply the signal as AC coupled as shown in the attached file.

    Could you please inform me about driving necesities for CLK input of AD9864?

    Abidin TASKIRAN

  • I want konw about AD9864 CLK IBIAS .when I set the 0X01 with 0x0C ,there is no effect,Vcm not change,

    I set 0x01 with 0x0C , the Vcm is still 3.3V ,it can not be set alone?

  • AD9864-saturation strength

    Hi,

    what is the ADC saturation signal strength of AD9864 at normal working conditions.?