• AD9863

    Hello.

    I have a question about AD9863. I'm planning to use its DACs to generate in IQ pair, and I do not need its ADCs. Is it safe to leave the ADCs' refercence decoupling pins open without affecting performance?

    Thank you very much in advance…

  • 3V at every TX-Output of AD9863

    Hello,

    I designed a Front End for a communication system with the AD9863. The Schematic and Layout were checked very well before it was manufactured, so I think it should work well. Its controlled by an FPGA. Without any programm running in the FPGA…

  • real sample rate of a two channel ADC

    Hi all,

    lets say I have a 2 channel (I and Q) front end like the AD9863 for a communication system.

    Belong the 50MSPS to each channel of the ADC so that I get 100MSPS after the data is multiplexed? Or when the clock is limited to 50MHz does each ADC…

  • RE: Clarification on AD - 9683

    Hello,

    Only the EVB with FMC connector is available.  Note, should the AD9863 EVB  not available at this time...........the AD9467 is also an option.

    wiki.analog.com/.../ad9467

  • RE: RFID SAW Reader

    The ADF9010 is designed as an RF front-end for an RFID reader system compliant to the EPC global

    RFID standards and can operate across a range of 840MHz to 960MHz.

    Figure 27. gives the applications diagram of the full transceiver which you would need…

  • RE: AD9683-250EBZ JESD204B Link Synchronisation

    Hello,

    A JESD 204B and FPGA expert may put better comments on this JESD interface related topic. Below is about AD9683 ADC side,

    For the clock to ADC, 200MHz is okay since AD9863 supports a differential clock between 40 MHz and 625 MHz. The required clock…

  • RE: RX LOs  independent? How many bits in ADC?

    Rx channels share the same LO. They cannot be configured for 2 different frequencies. They can receive signals separated within 100MHz.

    In AD9371 DAC is 14 Bit and ADC on receive and Observation path is 16 bits. You cannot compare performance with stand…

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