• RE: Unable to create iiobuffer : No such device or address

    Hi DragonB,

    Can you provide me the github link for Linux version 4.9.0-g87beab60b2b9 source.

    This version is stable and no issues . I want source for modifing ad9860 settings at driver level.

    With Regards,

    C P Umashankar

  • RE: AD9854 Interface with BF537 via Parallel Port.

    On BF537, PPI can operate at up to SCLK/2 rate. Assuming you have set SCLK to max value-i.e133MHz, then PPI in your application can operate at 66.67MHz max.

    Iooks like in EE-162, AD9860 has been interfaced to EBIU of the processor.

  • RE: Dual ADC Aquisition with PPI Interface

    Hi,

    Sorry, as I don't have any information regarding  which ADCs have evaluation boards available or non-obselete. You can  check with another ADC AD9860 which may suit your application, but as I  said I am not aware of the evaluation board availability…

  • RE: Can FMCOMMS6 acquire a 210 MHz wide Signal?

    Hello,

    Perhaps a 1 GSPS ADC like the AD9680 would be a better choice in IF sampling the two OQPSK signals at IF's of 655 and 785 MHz.  The AD9680 also includes two DDC such that this function can also be removed from the FPGA.   Since OQPSK does not…

  • Questions about the error “Timed out while attempting to fill FIFO (s)”

    Hello.
    I tried to observe the FFT using the canvas [AD9680 FFT] setting in the VisualAnalog software, but the Graph-AD9680 FFT remains blank.
    The message “ADC Data Capture: Error: Timed out while attempting to fill FIFO(s).” is displayed.…
  • RE: Connect IIO to ADC-SOC Cyclone 5 Cortex A9

    Hi Michael,

    after reading more docs, I think i understand it a bit better, but maybe you can advise me a bit.

    IIO and libio are only a linux thing and doesn't depend on the FPGA correct? And it is working remote via ethernet and usb and direct on the…

  • Length Matching requirement for JESD204B

    Hi All,

    I am working on AD9680 ADC, which is using JESD204B subclass 1 for data transfer. We made custom board which has AD9860 ADC and HMC7044 for clocking. In our setup receiver is Xilinx FPGA Board(zynq ultrascale+). 

    I have few queries  for length…

  • Balun

    Hello,

    I have a doubt about how to use the baluns. I have seen in aplication notes that, in the evaluation boards, if you have a SMA conector (like an input or output to the PCB) it's used the balun to convert the unbalanced input (ANNTENA) to a balanced…

  • Achieving Wideband RF Performance without Interleaving Artifacts

    Being able to discern a signal from the noise is a key aspect of many signal acquisition systems. Whether it is a defined telecommunications protocol, a radar sweep, or measurement instrumentation, acquiring and deciphering weak signals is at the heart…

  • RE: 请问AD9862的问题

    您好!

    看了您第一张图,应该是Iout输出,即高速DAC输出信号,即模拟电流信号。但是看您示波器截屏,像是还是由脉冲信号组成的正弦信号。因此建议您旁路其他功能,仅使用DAC,输入正弦数字信号,看输出是否是良好的正弦波。此外,建议您检查DAC模拟输出电路设计。附件为AD9862的评估板原理图,建议您参考其DAC模拟输出电路设计。