FAQ
Hi,
I was working in quadrature mode at 200 msps with ref clk 50Mhz using pll multiplier . I have configured the registers accordingly and even got the output successfully with shifting but later on the output was not fine and checked the pdclk it is…
Hello,
I am trying to work with two of AD9857 DDSs in a synchronized way.
In order to do that, at the same time, REFCLK, DATA, etc,
The problem I find is that latency of output will differ 1 PDCLK as Figure 33 and Figure 34 in the datasheet,
Is there…