Unlike some of our newer generation devices, the AD9857 does not a feature allowing you to clear the phase accumulator. For the AD9857, the only way to guarantee that the accumulator is at zero-phase is to reset the device, but that tends to be problematic…
AD9857 System Clock fsysclk = 198MHz, configure the AD9857 output 21MHz, 42MHz, 60MHz,the output is very good, using a spectrum analyzer observed spectrum is also very good, but when the frequency is 65MHz , the sine wave distortion , There is a spectrum…
We are using AD9857 in our DVB-T modulator board. Now it could work, but the output of AD9857 is too low. It is -76dbm. (Measured using a Spectrum Analyzer. ). Could you help me? Thanks. The schematic is attached.
Are you using the AD9857 evaluation board or is this a custom board?
We are using AD9857, so do u know the levels i asked?
first off all so much thanks for reply,
1, we are driving reset as low from fpga.
2. Bcoz ad9857 configered in single tone mode.i think no need to drive TXEN am i rite?
can you plz tell me what and all inputs we should give to ad9857 to…
I have my AD9857 with the next configuration:
I am using AD9857 with a single REFCLK input of 146.2857MHz with very good CMOS levels.(i have diffclken connected to gnd)
I have a 2K resistor in pin RSET.
Iout = 39.93/RSET, So Iout level should be 20mA…
I am trying to work with two of AD9857 DDSs in a synchronised way.
In order to do that,
at the same time, REFCLK, DATA etc ,
I configure these DDSs performing an automatic synchronisation.
The problem I find is that, after powering up them…