• ad9850

    ad9850的晶振是125Mhz,晶振波形没问题,但是ad9850输出波形是62.5Mhz,峰峰值为1.5V左右,程序不能控制频率,请问这是什么原因导致的

  • AD9850

    Hi there,

    My customer is using AD9850 to generate ultrasonic sinewave of 137KHz with an 100MHz reference clock in. In most cases, it works well. However, sometimes it fails to output sine wave. Instead, it outputs non-regular waveforms. When it fails…

  • 求助,AD9850工作一段时间实效原因

    我使用DSP2812来控制AD9850,DSp2812的GPIOB口作为控制端直接接入AD9850,AD9850采用3.3V供电,晶振100MHz在调试过程中,AD9850输出波形正确,峰峰值600mV+,但是执行一段时间(10min-1h不等)后AD9850的输出就没有了,能不能帮我分析一下原因

  • RE: AD9850 randomly stops generating signal - is this normal?

    Is the AD9850 board mentioned above an ADI AD9850 evaluation board or is this your board design? If your board design, can you send a schematic of the hookup if you're still having issues. Note, I would recommend using a 10uf on the each supply and 0…

  • Using one oscillator to supply MCLK for 4 AD9850

    This is David Guo from CAST,Beijing.

    If there are 4 pics AD9850 in one board, is it OK to use one oscillator to supply MCLK for 4 AD9850? What's the Drive Capability requirement of MCLK?

  • AD9850 questions

    We design and prototype a signal generator. One of the requirements is precise
    amplitude control. We are considering a design based on AD9850 followed by
    AD8370. We propose to replace the Rset resistor on pin 12 of the AD9850 by a
    mosfet…
  • RE: 3 x 400Hz Sine Generator

    The AD9834 could be used in such an application but some care must be used in designing the architecture to prevent latency issues. Please refer to the AN-587 apps note, attached. This document shows how to synhronise 2 or more AD9850/1s. The AD9834 can…

  • RE: AD9833

    Hi Tom,

    Just to add something to this discussion.

    This may be a synchonisation issue. You stated you are using the same MCLK for both AD9833s. The AD9834 is a better option for synchronising two DDS as it has the RESET pin function.

    In my experience…

  • RE: signal generate by the evel ad5930

    Hi Anas,

    Mclk is the external clock source for the part.

    The eval board populates a 50MHz clock source

    The maximum Mclk source clock for the AD5930 is 50MHz,

    If you want to increase the Mclk, you will need to move to the AD9850,

    http://www.analog…

  • RE: AD9850输出后的椭圆低通滤波器的设计

    您好,您的问题已经发送给相关专家了。您先浏览下AD9850相关的帖子。

    https://ezchina.analog.com/content?query=AD9850