• AD9781

    Three questions about AD9781:

    1. CLKP/N and DCIP/N -- CLKP/N is the main clock signals of the DAC. What is DCIP/N used for ? In the data sheet, it states DCI provides timing information about the parallel data and signals the I/Q status of the data. What…
  • AD9781 inputs VIA/VIB and outputs IQ

    HI all,

    I plan to use the AD9781 with 2 separate input data and IQ output data.

    May I know the 1st page of datasheet diagram, it shows VIA and VIB, it refers to 2 separate data streams right? Are they supposed to be interleaved into the D[15:0]?


  • AD9781 Inputs


    In AD9781 datasheet its not given what is the state of the inputs when the DAC is in reset state. After power ON do we need to drive some random LVDS data to inputs even if DAC is in reset? or we can leave the inputs in unknown state (inputs are…

  • AD9781 BIST


    I am using the BIST of AD9781 for testing DAC interface but I am facing some issues in that.

    Even if I am giving all 0s on the data lines of DAC then also the BIST when enabled picks up some random values and the result read is not 0.

    Is there…

  • AD9781 BIST


    I closed the earlier discussion as i thought the doubt is cleared. But still I am not able to figure out some problems.

    I am using offset binary now. I am giving the data vector followed by zeros and some of the results that I am getting are -

  • AD9781-Register values


    We are trying to load AD9781 registers via SPI. We are stuck at determining the SET, HLD and SMP delay. The table generation mentioned in datasheet is too tedious, and takes too much time. Are there any standard value for 200MSPS clock?


  • AD9781 - Clock Swing


    We are deriving clock for AD9781 from a LVPECL clock Buffer.

    The clock signal to CLKp and CLKn pins are shown in the attached figure (black & blue - CLKp &Clkn ; Red - Differential value). We can see the common mode voltage of 0.4 as required. However…

  • AD9781 Bist Feature


    If I am correct then in AD9781 the BIST mechanism samples the digital input data at the rising and falling edge of the CLK (DAC sampling clock) and keeps on adding them with the previously sampled data.

    Do we need to optimize the parallel port timing…

  • AD9781, ibis model?


    Do ADI have an ibis model for the AD9781, High Speed DAC?


  • Reset of AD9781


    in the datasheet of AD9781 it is given that it requires a positive pulse for getting reset. but after power on if the reset pin is kept high for 1us or more and after 10ns SPI is programmed then this chip will work or not ?

    the waveform at the…