• Getting the AD9780 Pspice model


    I want to using AD9780,81,83 series DACs as baseband I/Q signal processing unit.

    Can I get the Pspice model of AD9780 series?

    Or is there any method for using AD9780 with OrCAD simulator?

    I want to simulate the AD9780 with my circuit design…

  • higher update-rate and pin-to-pin compatible with ad9780

    we design signal generator with AD9780, and we want to using a higher update-rate and pin-to-pin compatible with AD9780, please recommend one DAC.

    thank you

  • RE: AD9780's default SMP, SET, and HLD

    There are no defualt values because the SMP id dependednt on the delay from DCO to your ASIC  or FFGA Plus dleyat thru the ASIC or FPGA and plus the dealy back to our AD9780. You can probably try a few values of SMP and find several that work without building…

  • RE: Using the AD9122 as independent 2CH DAC

    I beleive the only pats we have that can support this are the AD9783,1,0 (16,14,12 Bit family). These parts have a mix mode that allows you to output signals in the 2nd nyquist zone with higher signal levels but they don't have any modulation capability…

  • RE: AD9780 LVDS interface  impedance

    Yes the AD9780 integrates the internal 100 ohm termination resistor.


  • Latency of the AD9783,AD9781,AD9780 Dual DACs

    What is the Latency of the AD9783, AD9781, AD9780 DAC family and is it fixed  is there some sort of FIFO used in the itnerface?

  • which clock should be used to send data to AD9780?

    I have an FMC with AD9780. When I send data to it, two possible clock in FPGA can be used:

    1. The clock from DCO of AD9780

    2. Another clock which is derived from the sampling clock and fed into FPGA

    Which clock should I use for OSERDES in FPGA? Does…

  • The output waveform of AD9780


    I am using AD9780 at 300MSPS, and output 100MHz and 7MHz sinusoidal waveform.

    Are these waveforms normal?

    Or are they too noisy?

    Chao Xiang

  • DCIP/N and DCOP/N of AD9780

    In the datasheet of AD9780, the voltage level of those pins are not stated.

    Are them LVDS as the data input pairs?

    Or same as CLKP/N pair?


    Chao Xiang