• AD9779A操作

    你们好,

    我们正在使用AD9779A进行设计,有如下疑问:

    (1) 使用AD9779A的数据时钟信号(DATACLK)作为FPGA内部PLL的参考时钟,再用FPGA PLL产生的时钟信号把数据打出,请问FPGA PLL产生的时钟信号和AD9779A的数据时钟信号的相位关系?

    (2) AD9779A使用双端口模式,请问FPGA发送数据的时候,只要把AD9779A的TXENABLE管脚置为高电平,发送完成把TXENABLE
    管脚置为低电平,这样就ok?

    (3)  AD9779A的SPI接口: 当使用单字节传输的时候…

  • AD9779A 电流

    AD9779A  CVDD18电源总共需要多大的电流?DVDD18电源总共需要多大电流? datasheet上没有找到。

    谢谢!

  • AD9779A application

    Here we have a request in the application of high speed DAC. We’d
    like to use AD9779A, it’sthe dual DACs for I and Q output. If we use one port of it just as a direct IF
    DAC, the bandwidth is 100MHz, center frequency is 312.5MHz, is it possible?

    Objective…

  • AD9779A Timing Optimization

    I have a couple of questions regarding the Timing Optimization feature of the AD9779A DAC:

    - The datasheet states "The Data Timing Margin[3:0] variable determines how much before and after the actual data sampling point the margin test data are latched…

  • AD9779A close in noise

    Hi, All!

    I have measured the output spectrum of the AD9779A running at 155.52MHz (the internal PLL is DISABLED). The DAC is clocked from the clean source (ABLNO-V-155.52 crystal oscillator). I see a very strange noise shape close in to the carrier (see…

  • AD9779A automatic timing optimization

    I'm using automatic timing optimization mode of AD9779A.

    According to the datasheet, DATACLK Delay is increased if a setup error is detected.

    In my test board, interrupt reg keeps showing setup error (data timing error IRQ=1 & data timing error…

  • What is the relationship between AD9779A input frequency and output frequency

    AD9779A use consultation: Use 80M clock to drive the data interface of AD9779A, input data bit 2MHz sine wave, the register of address 0x01 is configured as 0x84, the register at address 0x02 is configured as 0x1C, and the register at address 0x03 is…

  • AD9779A管脚SYNC_I_P/SYNC_I_N

    请问不使用AD9779A的管脚SYNC_I_P/SYNC_I_N时,这两个管脚怎么处理?

    谢谢!

  • AD9779A emissions issue

    I’m running 160MHz in to REFCLK and configured the part to bypass its PLL, so internal DACCLK runs at 160MHz.

    I’m seeing a large 320MHz RF Emissions from the AD9779(A) part, which is causing my product to fail FCC. (See attached, measured with sniffer…

  • Max Current of AD9779A

    What is the max current of AD9779A  CVDD18 power? the max current of DVDD18 power?


    Thanks.