• Request for advice on layout AD9767


    I'm using DAC AD9767 for my project. It run at 125MHz clock.

    In datasheet, analog device recommended that data line should be route as stripline for clean signal. I have concern that when I route as stripline, I have to use via to change layer…

  • AD9767: Load range

    If I increase the output load resistors, what is the maximum output voltage
    that can be guaranteed?


    IOUTFS is in the range of 2mA to 20mA and the voltage IOUTAx and IOUTBx needs
    to be kept within the compliance range -1.0V to +1.25V. Therewith…

  • AD9767: Input timing for interleaved mode

    This is to verify AD9767 functionality in interleave mode. 

    Figure 27 on page 15 of Rev C datasheet contains interleave block diagram. 

    Could you please confirm that Port1,2 input latches are NOT synchronized with

    Prior to…

  • LTC5589 I/Q modulator with AD9767 TxDAC reference circuit design


    We are planning to use your LTC5589 I/Q modulator with AD9767 TxDAC for direct conversion of our modulated baseband signal upto 15MHz.

    We are planning to operate the DAC Sampling speed around 80 to 125MSPS and base-band symbol rate from 1MHz to 15MHz…

  • RE: AD9763 AD9765 AD9767 Interleaved mode with 125 MSPS update rate possible?


    Apologies for the delayed response. 

    The t_h specified in table 3 should be the hold time for rising edge of WRT and the data in (Please refer to figure 2). This does not specify the t_h* shown in figure 64 but rather shows that IQSEL should…

  • AD9767输出接口电路问题




  • AD9767 - Pins for stability

    Hello I have a question about this device. 

    In the datasheet of the AD9767, for the pins FSADJ1 and FSADJ2 it's recommended the use of a capacitor of 22nF and a resistor of 256r for stability purposes. What would be the impact of using 10nF and 100r instead…

  • RE: AD9767 SNR & ENOB

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • AD9767 Gain Control setting


    I followed the data sheet and used the same Rset value (2Kohm) at FSADJ1 and FSADJ2. Therefore, no matter how the GAINCTRL pin is set high or low, the DAC1 and DAC2 have the same value full-scale currents.

    In the experiment, I fed the DAC with a…