• AD9765 influence of the clocks

    > 1. Is it possible to clock the both DACs with different clocks like 33MHz and
    66MHz? What influence does this have on the specs, especially for the matching
    of the two channels when master/gain control mode with one resistor is used?
    > 2.…

  • AD9765 interfacing


    we are planning on integrating a couple (8) of AD9675 ADC converters in our design. The JESD204b IP block we'll be using from Xilinx, yet for the phy and data link layer, 

    Is it correct to state that we can use the AXI_AD9671 Ip core of AD, as both…

  • RE: AD9763 AD9765 AD9767 Interleaved mode with 125 MSPS update rate possible?


    Apologies for the delayed response. 

    The t_h specified in table 3 should be the hold time for rising edge of WRT and the data in (Please refer to figure 2). This does not specify the t_h* shown in figure 64 but rather shows that IQSEL should…

  • RE: AD9229和AD9765芯片驱动程序

    This question has been closed by the EZ team and is assumed answered.
  • AD9765写信号及时钟信号的配置

    1.现在我需要使用两片AD9765同步输出4个电流。两片AD9765的WRT和CLK信号可共用吗?即两片的WRT1/CLK1和WRT2/CLK2 共同使用配置信号WRT/CLK,而不是分别接WRT1,WRT2,WRT3,WRT4,CLK1,CLK2,CLK3,CLK4。


  • AD9765如何设置差分输出


  • Can AD9763's NC pins (i.e. pin 33 & 34) be driven or must they be definitely left floating?

    Can AD9763's NC pins (i.e. pin 33 & 34) be driven or must they be definitely
    left floating?
    We have the option to fit the AD9763 or the AD9765 on the same board. When the
    AD9763 is fitted the DB0 & DB1 N/C pins (i.e. pins 33 and 34) are…

  • RE: AD9767 SNR & ENOB

    Hi -

    The AD9765 and AD9767 do not meet the spec for ideal dynamic range SNR = 6.02*N + 1.72 dB. Their dynamic range is limited by SFDR.