• RE: AD9764 output help

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • RE: 关于AD9764与FPGA通信的问题

    This question has been closed by the EZ team and is assumed answered.
  • RE: FPGA Reference Design for AD6644/AD6645 and AD9764 Data Converters

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • AD9764 Glitch Impulse

    Do you have more information on the AD9764 glitch impulse? For example, is it roughly symetric above and below steady state level? Is it proportional to FS set current? Any screen captures?

    BTW, nice DACs, used this line before, just never had to be…

  • AD9764如何让输出数据同步

    ADI工程师:

    最近做的项目中FPGA输出的三路数据(正弦波)经过DAC芯片(AD9764)输出波形;如何实现同步呢?芯片没有同步管脚,该怎么做呢?多谢指导!

  • 关于AD9764输出电压值与理论计算值的差异测试

     

     

    上图是我所设计的DA输出部分,想通过DA输出一个锯齿波,电压幅值在9V之间即+4.5V~-4.5之间。

    其中差分运放A8047的放大倍数是G=499/226=2.2倍左右,经过实际测试,这个运放的放大部分是没有问题的。

    AD9764方面的IOUTAIOUTB的输出有点问题,按AD9764的手册上的公式

    其中RLOAD即120欧姆电阻,Rset则是2K欧姆电阻,VREFIO采用芯片本身的基准电压1.2V。

     

    我先在数据端输入0时,按理论IOUTA端的电压应该是

  • AD768和AD9764的输出电流转电压的疑问

    这两款芯片都可以输出差分电流。我现在想转换成线性的电压输出。

    在AD768的芯片手册中有这么个图:

    手册中说,这样连接,放大器输出的电压在0~2V之间。但为什么我觉得是在-2~0V之间呢?IOUTA的电流范围是0~20mA,IOUTA引脚输出的电流不应该是流出DA芯片,流向放大器吗?这样算出的应该是-2V~0V吧

    下面的图24中,电流是流入DA芯片的。我想确认一下,按图23那样连,输出的电压信号会是0~2V还是-2~0V

    在AD9764的芯片中也有类似的问题。这样输出的电压值应该也是负值吧…

  • AD9764 Rload

    Hi,

    Considering the AD9764 evaluation board which is shipped with transformer coupled output option, the DAC output current is 2 to 20 mA, the output voltage compliance range is -1 to 1.25V (calculated from dac transfer fuctıon as : +-0.96V),the minicircuits…

  • Minimum Sampling Rate for AD9764

    Hi,

    In the AD9764 datasheet page 3 it is said that the Maximum Output Update Rate (fCLOCK) is minimum =125 MSPS.

    What is the minimum valid sampling rate for AD9764 ?

    Any help please.

    Thank you very much

    HIDIR ASKAR

  • AD9764 clock input and COMP2 voltage

    Hi ,

    I am feeding my AD9764 DAC using a 16 MHz clock generated by Xilinx Spartan3AN FPGA and the clock signal is a square wave with 800 mV mean and 1.36 Vpk-pk .

    Also i see about 2 V in the COMP2 pin of AD9764 but i must see 0 V although i connect it…