In the AD9764 datasheet page 3 it is said that the Maximum Output Update Rate (fCLOCK) is minimum =125 MSPS.
What is the minimum valid sampling rate for AD9764 ?
Any help please.
Thank you very much
Hi HIDIR -
The AD9764 CLOCK input will draw at most +/- 10 micro-amps. You may be abae to connect an FPGA clock output directly to the AD9764 CLOCK input. If not, using the NC7SZ32 as a buffer is also a good idea.
If you use the transformer circuit…
The AD6645 I/O are CMOS, ~100MHz, so the trace design will not be so critical as long as they are less than a few inches (<6). You can copy the traces from the layout of the product evaluation boards , The files for the AD6645 are located at…
Considering the AD9764 evaluation board which is shipped with transformer coupled output option, the DAC output current is 2 to 20 mA, the output voltage compliance range is -1 to 1.25V (calculated from dac transfer fuctıon as : +-0.96V),the minicircuits…
I have designed a DAQ borad including AD9764, AD6644 and it communicates with Xilinx Spartan 3AN FPGA through FX2 expansion connector.
As indicated in the attachments we can see the input&output connections and the clock signal (which is RC filtered…
I've attached a measured glitch impulse waveform done on the AD9764. Glitch impulse behavior is not characterized, has no limits and is unpredictable.
AD9764数据接口为并口， 兼容3V 5V,COMS电平，边沿触发
How can i obtain the required clock specifications ? Is it possible to obtain it from the Spartan 3AN FPGA or i will generate it outside and feed the FPGA and the ADC & DAC boards.
The AD9764 is pin for pin compatible with the AD9754. It is recommended for new designs. It operates the same as the AD9754. And has almost identical performance specifications to the AD9754. The packages are slightly different.