Hello,
I am working with AD9763 DVDD=AVDD=3.3V.
I would like to drive the digital inputs (CLK, WRT, DB) with 2.5V pins from FPGA (the VOH Min of the FPGA is 2V). According to the AD9763 datasheet "Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V is 2.1V" but…
About AD9763.
Can you tell me what I should do about unused pins if I use port1 only ?Unused pins are CLK2/IQRESET,WRT2/IQSEL,DB0-P2～DB9-P2/MSB,IOUTA2 and IOUTB2.Connecting to ground, power supply, or nothing?What should I do more except these?
Hi ,
Could you please let me know the –40°C to +85°C as Operating temperature same as Case temperature (Tcase) or is it Ambient Temperature.
Could you please let me know if there is any data with regards ThetaJC .
Thanking you
With best regards and…
My apologies I answered you based on the AD9961 and AD9963. The AD9761 and AD9763 were introduced in 1999. The AD9763 and AD9761 are not recommended for new designs. You can look for alternatives in the selection table for high speed DACs on www.analog…
Hello
What is AD9763 output state on power up ?
I think that this output state on power up is indeterminate.
Is my understanding correct ?
Now, our AD9763 output on power up is about 0 at IOUT1 and about full-scale output at IOUT2.
(We have not configured…
Hi,
is it possible to get an output update rate of 125 MSPS with the DAC family AD9763 AD9765 AD9767 in the Interleaved mode?
According to datasheet Rev G. the latch pulse width (t_LPW, t_CPW) must be at least 3.5 ns.
For the interleaved mode, a 250 MHz…
I'm adapting a design from a retired engineer with two discrete AD9705s being used for IQ modulation. I noticed that in an earlier design, he had used a single AD9763. Comparing both of these options, it seems that the two discrete AD9705s beat the AD9763…
Thanks for your reply.
From Fig 68, could I say that the ENOB of AD9767 is lower than AD9763 ?