• AD9746/9783: DAC analog signal peak power attenuation issues on AD9746/9783 Evaluation boards.

    Dear Experts,

    My customer is evaluation AD9746 and AD9783 with those evaluation boards and found some of the following technical issues with AD9746/9783 evaluation boards. Could you please review the following descriptions and then reply to the following…

  • RE: AD9746 + SDP-H1: temperature performances & bandwidth

    Hi Shine,

    Concerning your first answer, actually we have consistent results for DAC frequencies at 10 and 40 MHz. My issue concerns frequencies below 1 MHz, and in this case we are far below DAC clock / 4 !!

              => Do you have an explanation?

     Concerning…

  • AD9746 SFDR

    Hi

    I have a couple of questions about AD9746.
    Datasheet says that SFDR is 82, 70 and 66 dBc in the individual conditions.
    Do these values represent the specifications to 2nd/3rd harmonic distortion or not ?
    I wonder if these values represent the specifications…

  • AD9746 DAC Output

    Hi,

    I'm wondering If I can use this configuration using AD9746 DAc and ADA4937 Differential amplifier.

    I tried a simulation with NI Multisim

    This simulation does not make any sense to me. Why can't I see any cut off frequency on the magnitude…

  • EVAL-AD9746: data clock generation

    Hello,

    I use EVAL-AD9746 + AD-DAC-FMC-ADP + SDP-H1.

    I can't generate a vector (single tone as shown as example within UG-1624), because of the error message: "No data clock was detected"  

    On EVAL-AD9746, the PLL of AD9516, seems to be unlocked…

  • AD9746 High Speed DAC issue?

    Dear Sirs,

     

    We are using AD high speed DAC AD9746 on one of our board.
    The DAC is configured in single port mode with data coming from a FPGA. We are
    seeing some issues with clocking data into the DAC. From the datasheet it was
    not clear when the data…

  • Feasibility of LVPECL & LVDS CLK at AD9746

    Hello,

    My customer use AD9746 at their system and they should use LVPECL or LVDS CLK for this DAC.

    And they will use LVPECL clk source.

    Below are the voltage swing spec. of AD9746 clock input & clock sources.

    1. LVPECL:  0 to 2 V         (1.8VL - 2.2.VH…

  • Using the AD9746 as independent 2 CH DAC

    Hello,

    My customer wants to know if the AD9746's two DACs can be used independently.

    When transmitting two real data, is it possible to transmit them independently to each DAC ?

    Thanks a lot.

  • AD9746接口逻辑电平匹配

    各位大侠:
    我在做一个设计, 用altera的DE4开发板驱动AD9746 DAC. DE4接口的逻辑电平为2.5V CMOS,
    AD9746输入数字接口逻辑电平是3.3V CMOS, 不知DE4是否可以直接驱动AD9746?
    请指教, 谢谢!\

    请看datasheet中的图不是表示只能从3.3V转换到2.5V,不能从2.5V转换到3.3V吗?

  • AD9746 + ADRF6755 found lots of harmonic of sample clk

    hi,

    Now we use the AD9746 and ADRF6755 to make the modulation,

    we found lots of the harmonic of the sample clk, our sample clk is 120MHz,

    so we found 240MHz, 480MHz,720MHz...in the spectrum of the rf out of ADRF6755.

     

    the picture is how i connect…