• RE: Driver for AD9744 DAC chip

    Hi,

    Requesting some additional info on this old thread - I am trying to implement AD9744 interface in Zynq FPGA. Looking at the timing diagram (Fig.2) in the AD9744 data-sheet, the DB lines just need to meet the setup and hold time w.r.t. the rising edge…

  • On the problem of false trigger pulse output of AD9744 (TxDAC) after power on

    Hi,When I use the AD9744 (TxDAC),I find that this component will generate a  false trigger output  pulse after power on. The amplitude of the false trigger pulse up to about 2V. This is harmful to my load circuit. But when I configure this TxDAC in a sleep…

  • RE: AD9744 power on reset

    Assumed answered offline.

  • AD9744 output bias voltage

    Hello

    There are some conventional DAC interfaces as shown below:

    https://www.analog.com/en/analog-dialogue/articles/buffering-the-output-of-high-speed-dacs.html

    TIA approach:

    or

    Difference amplifier approach:

    Actually I have used a FDA instead of a…

  • AD9744 clock input condition

    Hello

    Analog Experts I'm here after lots of challenging! Please help me.

    I have generated a LVDS clock with AD9508 and applied the generated clock to the AD9744 in Differential mode and DC-coupled mode.

    the swing at 100MHz is 730mV

    and the Vcm=1.…

  • AD9508 and AD9744 (DAC)

    Hi

    Analog experts I really need your help. it seems my thesis is going to hell or paradise!

    I have concluded a result at the end of this page. is it OK?

    according to the AD9508's datasheet:

    the output swing is as shown below:

    and the output offset…

  • RE: AD9744

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • how to connect AD9744 to gpga?

    hi,

    My problem is about how to provide clk to AD9744.

    1. Connect AD9744 CLK/CLKB to FPGA clk-able pins and the DAC clock is provided through MMCM in FPGA.

    2. Using a clock generator ( such as AD9517 ), and provide DAC converting clock and the same clock…

  • AD9744 digital data at LVCMOS 2.5V

    I am wondering if the DAC AD9744 can be driven from a digital source of 2.5V data signals.

    the Datasheet specifies 3 Volt as typical VIH level for digital data and the minimum set at 2.1 Volt.

    Is the AD9744 DAC still stable and without loosing performances…

  • AD9744的Clock Input setting.

    您好,

    我們使用AD9744作一個Voltage controller.

    在SOIC/TSSOP package的 pin 28_Clock腳,它需要輸入怎樣的訊號呢?

    在Datasheet中我不太明白這pin的要求是什麼。

    在32-Lead LFCSP package的CLK+-又是要輸入怎樣的訊號呢?

    Thanks.