• AD9742/AD9744 Exposed Pad

    Reading through the AD9742's datasheet I cannot find what the exposed pad
    should be tied to?

     

    The Exposed Thermal Pad must be soldered to copper pour on top surface of PCB
    for mechanical stability and must be electrically tied to low impedance…

  • AD9742 Spice Model

          Dear all,

          I need to spice model of AD9742. I can find IBIS model but it isn't useful for me. Could you provide spice model of AD9742? Thanks in advance.

  • AD9742 output buffer

    Hi,

    I'm working with AD9742 DAC at 48Msps with full-scale output set to 20mA. Previously our design used 50ohm resistors as current-to-voltage converter followed by Op-Amp buffers. Currently we're exploring to feed the DAC output into Op-Amp summing junctions…

  • RE: AD9742设置电流输出无效

    你好,我们现在遇到了与您相类似的问题,希望您可以给与一些帮助。

    首先,您最后还是采用外部参考2.5V的吗?还是进行了修改?

    其次,您后面能修改输出电流又是做了哪些改动?

  • RE: [AD9742]Could you teach MIN, TYP, and MAX at the shingle-end input?

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • 关于AD9742时钟连接方式的问题

    请教各位前辈,R4和R5的作用,以及添加DVDD的作用

  • AD9742 CLK+ input voltage

    Hello.

    It is a question concerning data sheet page 14 CLK INPUT(LFCSP Package) of AD9742.

    Single-ended clock input mode, CLK + input has been described as rail-to-rail.

    How many input voltage is rail-to-rail?

    (AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD =…

  • AD9742 External voltage reference

    Am I correct i thinking that I cannot use an external voltage reference with an AD9742ACPZ as the REFLO signal is not available with this LFCSP_WQ package? Whereas the REFLO signal is available with the AD9742ARZ TSSOP package.

    My reason for wishing…

  • [征文] 求救!关于AD9742的无输出问题。

    求救版主,在目前的PCB板上使用了贵公司的AD9742这一产品,目前遇到的情况是供电正常,3.3V
    的数字部分、模拟部分电压,只是由于疏忽忘了加去耦电容;12位数字输入由FPGA芯片提供、FCLOCK也由FPGA提供,50MHz。输入的12位数字信号频率为
    500KHz,目前发现有输入,无输出。其它部分均按照数据手册来的,IOUTA、IOUTB接到T1-1T KK81 想得到电压输出。无论是在T1-1T
    KK81的输入端还是输出端均无电压(不到2mV),想问问是什么个原因。谢谢!