• AD9739

    Dear Sir/Madam,
    Currently , I do an experiment with  multi-chip high-speed DAC AD9739 , but when measuring the DAC output signal
    …
    • attachments.zip

  • AD9739

    Dear Sir/Madam,

    I am using teh EVB of AD9739, and wonder clarifying some puzzles

    1. How does the AD9739 implement up-conversion,

    2  whether the input signal of AD9739 shoule be real signal, could it be complex signal

    3. whether or not AD9739 has integrated…

  • AD9739: FPGA selection

    Q 

    Since AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS using dual
    LVDS data ports, what host processor can we use to send data to AD9739 and how
    to connect the host processor for example a FPGA with AD9379? Could you please
    …

  • AD9739问题

    我们目前在做一个超宽带的项目，信号带宽528MHz发端送给射频的信号采样率为2.112Gbps,由于是I Q两路送入射频，所以我们的硬件板上有两片AD9739,在FPGA内部我们的数据速率是132Mbps,因此I Q各有16路并行数据，I路数据经过两个1分8的Oserdes送入AD9739的奇偶两路，Q路也做同样处理。DCI时钟和data都是Oserdes产生的，通过配置两片AD9739同步，主片和从片的寄存器回读数据正确，下图为长时间测试的两路波形的余晖图。

    然而下图为我们在2.112G的AD外部采样时钟情况下的OFDM符号…

  • AD9739: IRQ clearance

    Q 

    I am interfacing two AD9739 DAC's with VIRTEX-5. In the datasheet of AD9739 at
    PAGE NO. 49 under the section of INTERRUPT REQUESTS, it is given that --"If the
    pin is used to determine that an interrupt has occurred, it is also necessary…

  • AD9739   synchronization

        I have made a design in which ADCLK846 is used as the synchronizing clock destribution IC between two AD9739s . It seems that the output to output skew of ADCLK846 (Max 65ps) is two large to synchronizing AD9739s . Because the sync controller of  the…

  • AD9739 SPI issues

    Hi,

    I have experienced some problems with AD9739 SPI control and I would like to find out if these are known issues or maybe I did something wrong.

    1. The IRQ bits in register 4 (IRQ) cannot be cleared. I checked register 0x21 and 0x2a and verified…

  • AD9739: multichip synchronization

    Q 

    I have an application which require the two DAC's output phase difference
    should be smaller than 3 degree, If I use design synchronization circuit shown
    in  Figure 1, and DACLCK is 1GHz, AD9739's output may be several MHz ~ 400MHz, …

  • AD9739 evaluation board

    Hi everyone.

    Just a little question: when looking at the AD9739-R2-EBZ BOM, we can read lines like this:

    4 14 C3-C10, C31, C33, C51, C56, C76, C77 OBSOLETE - USE E007200/A004-0011-06 6 .1UF PHYCOMP …

  • AD9739 single port mode

    Hello!

    Can AD9739 be operated in single port mode (e.g. DB1[13:0] unused)?

    Is it okay to leave the pins of unused data port unconnected?

    Thanks in advance.