• AD9739 noise floor fluctuation

    Use DDS module of FPGA to generate data and output 600M signal through AD9739.. The noise floor of the output signal is unstable and fluctuating.Click here to play this video

  • AD9739 Power Supply Sequence

    Is there a power supply sequence for the AD9739? Is it ok if the 3.3V rail comes up 20-40 ms after the 1.8V rail?


  • AD9739


  • RE: AD9739 output spurs

    The problem is solved. User must transmit  signal to AD9739 before configuring the chip.

  • AD9739: FPGA selection

    Since AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS using dual
    LVDS data ports, what host processor can we use to send data to AD9739 and how
    to connect the host processor for example a FPGA with AD9379? Could you please
    provide a…

  • AD9739: IRQ clearance

    I am interfacing two AD9739 DAC's with VIRTEX-5. In the datasheet of AD9739 at
    PAGE NO. 49 under the section of INTERRUPT REQUESTS, it is given that --"If the
    pin is used to determine that an interrupt has occurred, it is also necessary…

  • AD9739: multichip synchronization

    I have an application which require the two DAC's output phase difference
    should be smaller than 3 degree, If I use design synchronization circuit shown
    in  Figure 1, and DACLCK is 1GHz, AD9739's output may be several MHz ~ 400MHz,

  • improve your AD9739's SNR

    Do you find the signal integrity of data transfer to your AD9739 DAC isn't quite as perfect as you expect? Odd small temperature ranges in which SNR or BER is worse than expected? Then consider increasing “fine_del_skew” in register 0x13.…

  • AD9739: Output amplitude DC-offset

    Why is the difference in DC-offset so large between devices? How to avoid?


    The DC offset is a result of the balun, MABACT0039, only providing a DC short
    to the IN pin while the IP pin is connected to a 50 ohm load (as well as 90.9
    ohm resistor…