Use DDS module of FPGA to generate data and output 600M signal through AD9739.. The noise floor of the output signal is unstable and fluctuating.
Is there a power supply sequence for the AD9739? Is it ok if the 3.3V rail comes up 20-40 ms after the 1.8V rail?
Thanks.
The problem is solved. User must transmit signal to AD9739 before configuring the chip.
Do you find the signal integrity of data transfer to your AD9739 DAC isn't quite as perfect as you expect? Odd small temperature ranges in which SNR or BER is worse than expected? Then consider increasing “fine_del_skew” in register 0x13.…