• AD9234,AD9735 spice模型

    请问如何才能得到AD9234和AD9735的spice模型?谢谢!

  • RE: AD9735 LVDS input voltage range

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • 如何保证2片AD9735的同步

    我的设计中使用2片DAC(AD9735)产生I和Q基带信号,同时,AD4350产生2.4GHz本振。然后通过正交调制(选用ADL5385),产生载频为1.2GHz的调制信号。2片DAC时钟由AD9516提供600MHz时钟。FPGA为2路DAC输出IQ数据,该数据保存在一片ROM中,从而保证IQ基带信号的严格对起。现在发现,2片AD9735的输出发生错位,错位0~4个DAC时钟周期。而且,每次上电后,错位情况都不一样。但是,上电后,错位保持不变。DAC的配置:每次上电后,同时对AD9735进行硬件复位…

  • BIST AD9735

    Hi,

    I just received an evaluation board for the AD9735-DPG2-EBZ and i'm trying to perform a BIST test.
    I installed all the software needed to download vectors into the DPG2 and the AD9735_SPI.exe to control the DAC's register from SPI.

    My question…

  • Datasheet errors in the AD9736/5/4

    Question 1)
    Is the datasheet 288522419AD9734_5_6_0.pdf the latest version? There seem to be
    pinout errors on page 54 og 68.

    Question 2)
    What connections are reccommended for the 2 unused bits in this 12-bit device?
    I assume I want to drive DB2…

  • Low Latency High-Speed ADC and DAC

    Hi All,

    One of my customer is looking for low latency high-speed ADC and DAC.

    His application is to capture high frequency signal by high-speed ADC and the data is processed by FPGA and output control signal from the FPGA and is converted to high-speed…

  • TAGS LIST: Data Converters

    AD693
    AD5410
    AD5412
    AD5420
    AD5422
    AD5735
    AD5755
    AD5755-1
    AD5737
    AD5757
    AD5421
    AD421
    AD5758
    AD7569
    AD7669
    AD7868
    AD7869
    AD5593R
    AD5592R
    AD5940
    AD5941
    AD7293
    AD7294-2
    AD7292
    AD5590
    AD7294
    L…
  • RE: 超级干货——DAC接口基本原理

    DAC数据输入考虑因素

    最早的单芯片DAC几乎不包含逻辑电路,且数字输入必须维持并行数据,才能维持数字 输出。而今,几乎所有DAC都会被锁存,且只需向其中写入数据,而不用去维持。有些 器件甚至具有非易失性锁存器并可在关断时记住设置。

    DAC输入结构存在无数变化形式,本文将不一一介绍,但几乎所有都称为“双缓冲”。栓 缓冲DAC具有两组锁存器。数据最初锁存在第一级中,然后传输到第二级,如图8所示。 这种配置非常有用,具体有以下几种原因。

    图8:双缓冲DAC允许复杂输入结构和同步更新

    首先…