I believe the settling time will be similar to the AD9114 which is specified to settle to 0.1% in 11.5ns, but I will need to confirm with out design engineers.
There is information in the datasheet regarding making the timing deterministic. Please see the "Estimating the Overall DAC Pipeline Delay" section of the datasheet. There is a slight update in process needed for this section which I have copied and corrected…
What is the purpose of the CMLI and CMLQ pins on the AD9717 and AD9117 DAC famlies and where do they need to be connected?
Some high speed DAC have options for auto-calibration. Why and when should I use this option?